mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
2264 lines
150 KiB
C
2264 lines
150 KiB
C
#ifndef __EXYNOS8890_PMUSFR_H__
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#define __EXYNOS8890_PMUSFR_H__
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#include "S5E8890-sfrbase.h"
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#define OM_STAT ((void *)(PMU_ALIVE_BASE + 0x0000))
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#define RTC_CLKO_SEL ((void *)(PMU_ALIVE_BASE + 0x001C))
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#define PMU_SYNC_CTRL ((void *)(PMU_ALIVE_BASE + 0x0020))
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#define SFR_ACCESS_CONTROL_REG ((void *)(PMU_ALIVE_BASE + 0x0024))
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#define CLKREQ_PAD_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0028))
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#define PWREN_G3D_PAD_CONTROL ((void *)(PMU_ALIVE_BASE + 0x002C))
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#define CP_CTRL_NS ((void *)(PMU_ALIVE_BASE + 0x0030))
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#define CP_CTRL_S ((void *)(PMU_ALIVE_BASE + 0x0034))
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#define CP_STAT ((void *)(PMU_ALIVE_BASE + 0x0038))
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#define CP_DEBUG ((void *)(PMU_ALIVE_BASE + 0x003C))
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#define CP_DURATION ((void *)(PMU_ALIVE_BASE + 0x0040))
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#define CP2AP_MEM_CONFIG ((void *)(PMU_ALIVE_BASE + 0x0050))
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#define CP2AP_MIF0_PERI_ACCESS_CON ((void *)(PMU_ALIVE_BASE + 0x0054))
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#define CP2AP_MIF1_PERI_ACCESS_CON ((void *)(PMU_ALIVE_BASE + 0x0058))
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#define CP2AP_MIF2_PERI_ACCESS_CON ((void *)(PMU_ALIVE_BASE + 0x005C))
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#define CP2AP_MIF3_PERI_ACCESS_CON ((void *)(PMU_ALIVE_BASE + 0x0060))
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#define CP2AP_CCORE_PERI_ACCESS_CON ((void *)(PMU_ALIVE_BASE + 0x0064))
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#define CP_BOOT_TEST_RST_CONFIG ((void *)(PMU_ALIVE_BASE + 0x0068))
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#define CP2AP_PERI_ACCESS_WIN ((void *)(PMU_ALIVE_BASE + 0x006C))
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#define MODAPIF_CONFIG ((void *)(PMU_ALIVE_BASE + 0x0070))
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#define CP_CLK_CTRL ((void *)(PMU_ALIVE_BASE + 0x0074))
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#define CP_QOS ((void *)(PMU_ALIVE_BASE + 0x0078))
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#define ERROR_CODE_DATA ((void *)(PMU_ALIVE_BASE + 0x007C))
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#define ERROR_CODE_PERI ((void *)(PMU_ALIVE_BASE + 0x0080))
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#define MNGS_INTR_SPREAD_ENABLE ((void *)(PMU_ALIVE_BASE + 0x0100))
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#define MNGS_INTR_SPREAD_USE_STANDBYWFI ((void *)(PMU_ALIVE_BASE + 0x0104))
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#define MNGS_INTR_SPREAD_BLOCKING_DURATION ((void *)(PMU_ALIVE_BASE + 0x0108))
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#define APOLLO_INTR_SPREAD_ENABLE ((void *)(PMU_ALIVE_BASE + 0x0110))
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#define APOLLO_INTR_SPREAD_USE_STANDBYWFI ((void *)(PMU_ALIVE_BASE + 0x0114))
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#define APOLLO_INTR_SPREAD_BLOCKING_DURATION ((void *)(PMU_ALIVE_BASE + 0x0118))
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#define UP_SCHEDULER ((void *)(PMU_ALIVE_BASE + 0x0120))
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#define CENTRAL_SEQ_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x0200))
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#define CENTRAL_SEQ_STATUS ((void *)(PMU_ALIVE_BASE + 0x0204))
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#define CENTRAL_SEQ_OPTION ((void *)(PMU_ALIVE_BASE + 0x0208))
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#define CENTRAL_SEQ_OPTION1 ((void *)(PMU_ALIVE_BASE + 0x020C))
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#define CENTRAL_SEQ_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x0210))
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#define CENTRAL_SEQ_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x0214))
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#define CENTRAL_SEQ_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x0218))
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#define CENTRAL_SEQ_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x021C))
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#define SEQ_TRANSITION0 ((void *)(PMU_ALIVE_BASE + 0x0220))
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#define SEQ_TRANSITION1 ((void *)(PMU_ALIVE_BASE + 0x0224))
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#define SEQ_TRANSITION2 ((void *)(PMU_ALIVE_BASE + 0x0228))
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#define SEQ_TRANSITION3 ((void *)(PMU_ALIVE_BASE + 0x022C))
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#define SEQ_TRANSITION4 ((void *)(PMU_ALIVE_BASE + 0x0230))
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#define SEQ_TRANSITION5 ((void *)(PMU_ALIVE_BASE + 0x0234))
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#define SEQ_TRANSITION6 ((void *)(PMU_ALIVE_BASE + 0x0238))
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#define SEQ_TRANSITION7 ((void *)(PMU_ALIVE_BASE + 0x023C))
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#define CENTRAL_SEQ_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x0240))
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#define CENTRAL_SEQ_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x0244))
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#define CENTRAL_SEQ_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x0248))
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#define CENTRAL_SEQ_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x0250))
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#define CENTRAL_SEQ_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x0254))
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#define CENTRAL_SEQ_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x0258))
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#define CENTRAL_SEQ_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x025C))
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#define SEQ_MIF_TRANSITION0 ((void *)(PMU_ALIVE_BASE + 0x0260))
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#define SEQ_MIF_TRANSITION1 ((void *)(PMU_ALIVE_BASE + 0x0264))
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#define SEQ_MIF_TRANSITION2 ((void *)(PMU_ALIVE_BASE + 0x0268))
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#define SEQ_MIF_TRANSITION3 ((void *)(PMU_ALIVE_BASE + 0x026C))
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#define SEQ_MIF_TRANSITION4 ((void *)(PMU_ALIVE_BASE + 0x0270))
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#define SEQ_MIF_TRANSITION5 ((void *)(PMU_ALIVE_BASE + 0x0274))
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#define SEQ_MIF_TRANSITION6 ((void *)(PMU_ALIVE_BASE + 0x0278))
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#define SEQ_MIF_TRANSITION7 ((void *)(PMU_ALIVE_BASE + 0x027C))
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#define CENTRAL_SEQ_CP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x0280))
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#define CENTRAL_SEQ_CP_STATUS ((void *)(PMU_ALIVE_BASE + 0x0284))
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#define CENTRAL_SEQ_CP_OPTION ((void *)(PMU_ALIVE_BASE + 0x0288))
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#define CENTRAL_SEQ_CP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x0290))
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#define CENTRAL_SEQ_CP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x0294))
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#define CENTRAL_SEQ_CP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x0298))
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#define CENTRAL_SEQ_CP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x029C))
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#define SEQ_CP_TRANSITION0 ((void *)(PMU_ALIVE_BASE + 0x02A0))
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#define SEQ_CP_TRANSITION1 ((void *)(PMU_ALIVE_BASE + 0x02A4))
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#define SEQ_CP_TRANSITION2 ((void *)(PMU_ALIVE_BASE + 0x02A8))
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#define SEQ_CP_TRANSITION3 ((void *)(PMU_ALIVE_BASE + 0x02AC))
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#define SEQ_CP_TRANSITION4 ((void *)(PMU_ALIVE_BASE + 0x02B0))
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#define SEQ_CP_TRANSITION5 ((void *)(PMU_ALIVE_BASE + 0x02B4))
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#define SEQ_CP_TRANSITION6 ((void *)(PMU_ALIVE_BASE + 0x02B8))
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#define SEQ_CP_TRANSITION7 ((void *)(PMU_ALIVE_BASE + 0x02BC))
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#define SEQ_TRANSITION8 ((void *)(PMU_ALIVE_BASE + 0x02C0))
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#define SEQ_TRANSITION9 ((void *)(PMU_ALIVE_BASE + 0x02C4))
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#define SEQ_TRANSITION10 ((void *)(PMU_ALIVE_BASE + 0x02C8))
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#define SEQ_TRANSITION11 ((void *)(PMU_ALIVE_BASE + 0x02CC))
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#define SEQ_TRANSITION12 ((void *)(PMU_ALIVE_BASE + 0x02D0))
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#define SEQ_TRANSITION13 ((void *)(PMU_ALIVE_BASE + 0x02D4))
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#define SEQ_TRANSITION14 ((void *)(PMU_ALIVE_BASE + 0x02D8))
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#define SEQ_TRANSITION15 ((void *)(PMU_ALIVE_BASE + 0x02DC))
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#define SEQ_MIF_TRANSITION8 ((void *)(PMU_ALIVE_BASE + 0x02E0))
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#define SEQ_MIF_TRANSITION9 ((void *)(PMU_ALIVE_BASE + 0x02E4))
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#define SEQ_MIF_TRANSITION10 ((void *)(PMU_ALIVE_BASE + 0x02E8))
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#define SEQ_MIF_TRANSITION11 ((void *)(PMU_ALIVE_BASE + 0x02EC))
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#define SEQ_MIF_TRANSITION12 ((void *)(PMU_ALIVE_BASE + 0x02F0))
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#define SEQ_MIF_TRANSITION13 ((void *)(PMU_ALIVE_BASE + 0x02F4))
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#define SEQ_MIF_TRANSITION14 ((void *)(PMU_ALIVE_BASE + 0x02F8))
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#define SEQ_MIF_TRANSITION15 ((void *)(PMU_ALIVE_BASE + 0x02FC))
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#define SEQ_CP_TRANSITION8 ((void *)(PMU_ALIVE_BASE + 0x0300))
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#define SEQ_CP_TRANSITION9 ((void *)(PMU_ALIVE_BASE + 0x0304))
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#define SEQ_CP_TRANSITION10 ((void *)(PMU_ALIVE_BASE + 0x0308))
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#define SEQ_CP_TRANSITION11 ((void *)(PMU_ALIVE_BASE + 0x030C))
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#define SEQ_CP_TRANSITION12 ((void *)(PMU_ALIVE_BASE + 0x0310))
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#define SEQ_CP_TRANSITION13 ((void *)(PMU_ALIVE_BASE + 0x0314))
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#define SEQ_CP_TRANSITION14 ((void *)(PMU_ALIVE_BASE + 0x0318))
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#define SEQ_CP_TRANSITION15 ((void *)(PMU_ALIVE_BASE + 0x031C))
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#define IDLE_IP0 ((void *)(PMU_ALIVE_BASE + 0x03E0))
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#define IDLE_IP1 ((void *)(PMU_ALIVE_BASE + 0x03E4))
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#define IDLE_IP2 ((void *)(PMU_ALIVE_BASE + 0x03E8))
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#define IDLE_IP3 ((void *)(PMU_ALIVE_BASE + 0x03EC))
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#define IDLE_IP0_MASK ((void *)(PMU_ALIVE_BASE + 0x03F0))
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#define IDLE_IP1_MASK ((void *)(PMU_ALIVE_BASE + 0x03F4))
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#define IDLE_IP2_MASK ((void *)(PMU_ALIVE_BASE + 0x03F8))
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#define IDLE_IP3_MASK ((void *)(PMU_ALIVE_BASE + 0x03FC))
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#define SWRESET ((void *)(PMU_ALIVE_BASE + 0x0400))
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#define RST_STAT ((void *)(PMU_ALIVE_BASE + 0x0404))
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#define AUTOMATIC_DISABLE_WDT ((void *)(PMU_ALIVE_BASE + 0x0408))
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#define MASK_WDT_RESET_REQUEST ((void *)(PMU_ALIVE_BASE + 0x040C))
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#define MASK_WRESET_REQUEST ((void *)(PMU_ALIVE_BASE + 0x0410))
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#define CPU_RESET_DISABLE_FROM_WDTRESET ((void *)(PMU_ALIVE_BASE + 0x0414))
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#define WDTRESET_LPI ((void *)(PMU_ALIVE_BASE + 0x0418))
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#define CPU_RESET_DISABLE_FROM_SOFTRESET ((void *)(PMU_ALIVE_BASE + 0x041C))
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#define RESET_LPI_TIMEOUT ((void *)(PMU_ALIVE_BASE + 0x0420))
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#define RESET_SEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x0500))
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#define RESET_SEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x0504))
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#define RESET_SEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x0508))
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#define RESET_SEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x0510))
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#define RESET_SEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x0514))
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#define RESET_SEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x0518))
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#define RESET_SEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x051C))
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#define WAKEUP_STAT ((void *)(PMU_ALIVE_BASE + 0x0600))
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#define WAKEUP_STAT2 ((void *)(PMU_ALIVE_BASE + 0x0604))
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#define WAKEUP_STAT3 ((void *)(PMU_ALIVE_BASE + 0x0608))
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#define EINT_WAKEUP_MASK ((void *)(PMU_ALIVE_BASE + 0x060C))
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#define WAKEUP_MASK ((void *)(PMU_ALIVE_BASE + 0x0610))
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#define WAKEUP_MASK2 ((void *)(PMU_ALIVE_BASE + 0x0614))
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#define WAKEUP_MASK3 ((void *)(PMU_ALIVE_BASE + 0x0618))
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#define WAKEUP_INTERRUPT ((void *)(PMU_ALIVE_BASE + 0x061C))
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#define WAKEUP_STAT_MIF ((void *)(PMU_ALIVE_BASE + 0x0620))
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#define EINT_WAKEUP_MASK_MIF ((void *)(PMU_ALIVE_BASE + 0x0624))
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#define WAKEUP_MASK_MIF ((void *)(PMU_ALIVE_BASE + 0x0628))
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#define EINT_WAKEUP_MASK1 ((void *)(PMU_ALIVE_BASE + 0x062C))
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#define MMC_CONWKUP_CTRL ((void *)(PMU_ALIVE_BASE + 0x0660))
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#define USB30PHY0_UDRD30_WAKEUP ((void *)(PMU_ALIVE_BASE + 0x0680))
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#define HSIC_WAKEUP ((void *)(PMU_ALIVE_BASE + 0x0684))
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#define USB20_WAKEUP ((void *)(PMU_ALIVE_BASE + 0x0688))
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#define HDMI_PHY_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0700))
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#define USBDEV_PHY_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0704))
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#define MIPI_PHY_M4S4_CONTROL ((void *)(PMU_ALIVE_BASE + 0x070C))
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#define MIPI_PHY_M4S0_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0710))
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#define MIPI_PHY_M0S4C_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0714))
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#define MIPI_PHY_M0S1_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0718))
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#define WIFI0_PHY_CONTROL ((void *)(PMU_ALIVE_BASE + 0x071C))
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#define WIFI1_PHY_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0720))
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#define UFS_PHY_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0724))
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#define SDCARD_PHY_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0728))
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#define DPTX_PHY_CONTROL ((void *)(PMU_ALIVE_BASE + 0x072C))
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#define MIPI_PHY_M1S0_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0730))
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#define MIPI_PHY_M0S2_CONTROL ((void *)(PMU_ALIVE_BASE + 0x0734))
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#define PPC_APOLLO ((void *)(PMU_ALIVE_BASE + 0x0740))
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#define PPC_G3D ((void *)(PMU_ALIVE_BASE + 0x0744))
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#define PPC_MIF0 ((void *)(PMU_ALIVE_BASE + 0x0748))
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#define PPC_MIF1 ((void *)(PMU_ALIVE_BASE + 0x074C))
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#define PPC_MIF2 ((void *)(PMU_ALIVE_BASE + 0x0750))
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#define PPC_INT0 ((void *)(PMU_ALIVE_BASE + 0x0754))
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#define PPC_INT1 ((void *)(PMU_ALIVE_BASE + 0x0758))
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#define PPC_INT2 ((void *)(PMU_ALIVE_BASE + 0x075C))
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#define PPC_DISP ((void *)(PMU_ALIVE_BASE + 0x0760))
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#define ALIVEIRAM_WRITE ((void *)(PMU_ALIVE_BASE + 0x0770))
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#define UPACG_AT_CMU ((void *)(PMU_ALIVE_BASE + 0x0790))
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#define INFORM0 ((void *)(PMU_ALIVE_BASE + 0x0800))
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#define INFORM1 ((void *)(PMU_ALIVE_BASE + 0x0804))
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#define INFORM2 ((void *)(PMU_ALIVE_BASE + 0x0808))
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#define INFORM3 ((void *)(PMU_ALIVE_BASE + 0x080C))
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#define SYSIP_DAT0 ((void *)(PMU_ALIVE_BASE + 0x0810))
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#define SYSIP_DAT1 ((void *)(PMU_ALIVE_BASE + 0x0814))
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#define SYSIP_DAT2 ((void *)(PMU_ALIVE_BASE + 0x0818))
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#define SYSIP_DAT3 ((void *)(PMU_ALIVE_BASE + 0x081C))
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#define PS_HOLD_HW_TRIP ((void *)(PMU_ALIVE_BASE + 0x0820))
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#define PS_HOLD_SW_TRIP ((void *)(PMU_ALIVE_BASE + 0x0824))
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#define PMU_SPARE0 ((void *)(PMU_ALIVE_BASE + 0x0900))
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#define PMU_SPARE1 ((void *)(PMU_ALIVE_BASE + 0x0904))
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#define PMU_SPARE2 ((void *)(PMU_ALIVE_BASE + 0x0908))
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#define PMU_SPARE3 ((void *)(PMU_ALIVE_BASE + 0x090C))
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#define ACK_LAST_CPU ((void *)(PMU_ALIVE_BASE + 0x0940))
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#define IROM_DATA_REG0 ((void *)(PMU_ALIVE_BASE + 0x0980))
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#define IROM_DATA_REG1 ((void *)(PMU_ALIVE_BASE + 0x0984))
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#define IROM_DATA_REG2 ((void *)(PMU_ALIVE_BASE + 0x0988))
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#define IROM_DATA_REG3 ((void *)(PMU_ALIVE_BASE + 0x098C))
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#define DREX_CALIBRATION0 ((void *)(PMU_ALIVE_BASE + 0x09A0))
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#define DREX_CALIBRATION1 ((void *)(PMU_ALIVE_BASE + 0x09A4))
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#define DREX_CALIBRATION2 ((void *)(PMU_ALIVE_BASE + 0x09A8))
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#define DREX_CALIBRATION3 ((void *)(PMU_ALIVE_BASE + 0x09AC))
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#define DREX_CALIBRATION4 ((void *)(PMU_ALIVE_BASE + 0x09B0))
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#define DREX_CALIBRATION5 ((void *)(PMU_ALIVE_BASE + 0x09B4))
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#define DREX_CALIBRATION6 ((void *)(PMU_ALIVE_BASE + 0x09B8))
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#define DREX_CALIBRATION7 ((void *)(PMU_ALIVE_BASE + 0x09BC))
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#define PMU_DEBUG ((void *)(PMU_ALIVE_BASE + 0x0A00))
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#define ARM_CONTROL_OPTION ((void *)(PMU_ALIVE_BASE + 0x0A04))
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#define BURNIN_CTRL ((void *)(PMU_ALIVE_BASE + 0x0A08))
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#define PMU_DEBUG1 ((void *)(PMU_ALIVE_BASE + 0x0A0C))
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#define PMUDBG_CENTRAL_SEQ_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F00))
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#define PMUDBG_CENTRAL_SEQ_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F04))
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#define PMUDBG_MNGS_CPU0_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F08))
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#define PMUDBG_MNGS_CPU1_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F0C))
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#define PMUDBG_MNGS_CPU2_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F10))
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#define PMUDBG_MNGS_CPU3_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F14))
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#define PMUDBG_APOLLO_CPU0_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F20))
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#define PMUDBG_APOLLO_CPU1_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F24))
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#define PMUDBG_APOLLO_CPU2_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F28))
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#define PMUDBG_APOLLO_CPU3_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F2C))
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#define PMUDBG_MNGS_L2_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F30))
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#define PMUDBG_APOLLO_L2_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F34))
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#define PMUDBG_MNGS_NONCPU_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F38))
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#define PMUDBG_APOLLO_NONCPU_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F3C))
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#define OTP_STATUS ((void *)(PMU_ALIVE_BASE + 0x0F40))
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#define MNGS_CPU0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1000))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1004))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1008))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x100C))
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#define MNGS_CPU1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1010))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1014))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1018))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x101C))
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#define MNGS_CPU2_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1020))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1024))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1028))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x102C))
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#define MNGS_CPU3_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1030))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1034))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1038))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x103C))
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#define APOLLO_CPU0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1040))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1044))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1048))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x104C))
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#define APOLLO_CPU1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1050))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1054))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1058))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x105C))
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#define APOLLO_CPU2_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1060))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1064))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1068))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x106C))
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#define APOLLO_CPU3_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1070))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1074))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1078))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x107C))
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#define MNGS_NONCPU_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1080))
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#define APOLLO_NONCPU_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1084))
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#define MNGS_DBG_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1088))
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#define CORTEXM3_APM_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x10A0))
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#define A7IS_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x10B0))
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#define DIS_IRQ_A7IS_LOCAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x10B4))
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#define DIS_IRQ_A7IS_CENTRAL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x10B8))
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#define MNGS_L2_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x10C0))
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#define APOLLO_L2_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x10C4))
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#define MNGS_L2_PWR_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x10D0))
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#define CLKSTOP_CMU_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1100))
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#define CLKRUN_CMU_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1104))
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#define RETENTION_CMU_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1108))
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#define RESET_CMU_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x110C))
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#define RESET_CPUCLKSTOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x111C))
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#define CLKSTOP_CMU_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1120))
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#define CLKRUN_CMU_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1124))
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#define RETENTION_CMU_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1128))
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#define RESET_CMU_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x112C))
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#define DDRPHY_CLKSTOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1130))
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#define DDRPHY_ISO_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1134))
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#define DDRPHY_SOC2_ISO_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1138))
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#define DDRPHY_DLL_CLK_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x113C))
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#define DISABLE_PLL_CMU_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1140))
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#define DISABLE_PLL_AUD_PLL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1144))
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#define DISABLE_PLL_CMU_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1160))
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#define RESET_AHEAD_CP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1170))
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#define TOP_BUS_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1180))
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#define TOP_RETENTION_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1184))
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#define TOP_PWR_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1188))
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#define CMU_PWR_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x118C))
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#define TOP_BUS_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1190))
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#define TOP_RETENTION_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1194))
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#define TOP_PWR_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1198))
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#define PSCDC_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x119C))
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#define LOGIC_RESET_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11A0))
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#define OSCCLK_GATE_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11A4))
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#define SLEEP_RESET_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11A8))
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#define LOGIC_RESET_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11B0))
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#define OSCCLK_GATE_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11B4))
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#define SLEEP_RESET_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11B8))
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#define MEMORY_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11C0))
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#define CLEANY_BUS_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11CC))
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#define LOGIC_RESET_CP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11D0))
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#define TCXO_GATE_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11D4))
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#define RESET_ASB_CP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11D8))
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#define RESET_ASB_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11DC))
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#define MEMORY_IMEM_ALIVEIRAM_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11E0))
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#define MEMORY_MIF_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11E4))
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#define LOGIC_RESET_DDRPHY_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11F0))
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#define RETENTION_DDRPHY_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11F4))
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#define PWR_DDRPHY_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x11FC))
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#define PAD_RETENTION_LPDDR4_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1200))
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#define PAD_RETENTION_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1204))
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#define PAD_RETENTION_JTAG_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1208))
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#define PAD_RETENTION_PCIE_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x120C))
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#define PAD_RETENTION_UFS_CARD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1210))
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#define PAD_RETENTION_MMC2_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1218))
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#define PAD_RETENTION_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1220))
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#define PAD_RETENTION_UART_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1224))
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#define PAD_RETENTION_MMC0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1228))
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#define PAD_RETENTION_EBIA_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1230))
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#define PAD_RETENTION_EBIB_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1234))
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#define PAD_RETENTION_SPI_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1238))
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#define PAD_RETENTION_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x123C))
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#define PAD_ISOLATION_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1240))
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#define PAD_RETENTION_BOOTLDO_0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1248))
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#define PAD_RETENTION_UFS_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x124C))
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#define PAD_ISOLATION_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1250))
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#define PAD_RETENTION_USB_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1254))
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#define PAD_RETENTION_BOOTLDO_1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1258))
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#define PAD_ALV_SEL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1260))
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#define XXTI_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1284))
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#define TCXO_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x128C))
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#define EXT_REGULATOR_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x12C0))
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#define EXT_REGULATOR_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x12C4))
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#define GPIO_MODE_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1300))
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#define GPIO_MODE_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1304))
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#define GPIO_MODE_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1308))
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#define GPIO_MODE_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1320))
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#define GPIO_MODE_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1340))
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#define CLKSTOP_OPEN_CMU_TOP_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1380))
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#define CLKSTOP_OPEN_CMU_MIF_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1384))
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#define CLKSTOP_OPEN_CMU_CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1388))
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#define CLKSTOP_OPEN_CMU_MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x138C))
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#define CLKSTOP_OPEN_CMU_G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1390))
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#define CLKSTOP_OPEN_CMU_DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1394))
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#define CLKSTOP_OPEN_CMU_CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1398))
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#define CLKSTOP_OPEN_CMU_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x139C))
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#define CLKSTOP_OPEN_CMU_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x13A0))
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#define CLKSTOP_OPEN_CMU_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x13A4))
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#define CLKSTOP_OPEN_CMU_ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x13A8))
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#define CLKSTOP_OPEN_CMU_ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x13AC))
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#define CLKSTOP_OPEN_CMU_MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x13B0))
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#define CLKSTOP_OPEN_CMU_DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x13B4))
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#define CLKSTOP_OPEN_CMU_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x13B8))
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#define CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1404))
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#define MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1408))
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#define G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x140C))
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#define DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1410))
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#define CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1414))
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#define AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1418))
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#define FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x141C))
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#define BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1420))
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#define ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1424))
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#define ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1428))
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#define MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x142C))
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#define DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1430))
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#define FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1434))
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#define CLKRUN_CMU_CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1444))
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#define CLKRUN_CMU_MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1448))
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#define CLKRUN_CMU_G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x144C))
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#define CLKRUN_CMU_DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1450))
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#define CLKRUN_CMU_CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1454))
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#define CLKRUN_CMU_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1458))
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#define CLKRUN_CMU_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x145C))
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#define CLKRUN_CMU_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1460))
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#define CLKRUN_CMU_ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1468))
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#define CLKRUN_CMU_ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x146C))
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#define CLKRUN_CMU_MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1470))
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#define CLKRUN_CMU_DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1474))
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#define CLKRUN_CMU_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1478))
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#define CLKSTOP_CMU_CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1484))
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#define CLKSTOP_CMU_MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1488))
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#define CLKSTOP_CMU_G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x148C))
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#define CLKSTOP_CMU_DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1490))
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#define CLKSTOP_CMU_CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1494))
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#define CLKSTOP_CMU_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1498))
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#define CLKSTOP_CMU_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x149C))
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#define CLKSTOP_CMU_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14A0))
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#define CLKSTOP_CMU_ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14A8))
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#define CLKSTOP_CMU_ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14AC))
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#define CLKSTOP_CMU_MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14B0))
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#define CLKSTOP_CMU_DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14B4))
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#define CLKSTOP_CMU_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14B8))
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#define DISABLE_PLL_CMU_CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14C4))
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#define DISABLE_PLL_CMU_MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14C8))
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#define DISABLE_PLL_CMU_G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14CC))
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#define DISABLE_PLL_CMU_DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14D0))
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#define DISABLE_PLL_CMU_CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14D4))
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#define DISABLE_PLL_CMU_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14D8))
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#define DISABLE_PLL_CMU_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14DC))
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#define DISABLE_PLL_CMU_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14E0))
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#define DISABLE_PLL_CMU_ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14E8))
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#define DISABLE_PLL_CMU_ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14EC))
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#define DISABLE_PLL_CMU_MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14F0))
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#define DISABLE_PLL_CMU_DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14F4))
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#define DISABLE_PLL_CMU_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x14F8))
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#define RESET_LOGIC_CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1504))
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#define RESET_LOGIC_MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1508))
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#define RESET_LOGIC_G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x150C))
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#define RESET_LOGIC_DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1510))
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#define RESET_LOGIC_CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1514))
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#define RESET_LOGIC_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1518))
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#define RESET_LOGIC_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x151C))
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#define RESET_LOGIC_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1520))
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#define RESET_LOGIC_ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1528))
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#define RESET_LOGIC_ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x152C))
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#define RESET_LOGIC_MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1530))
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#define RESET_LOGIC_DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1534))
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#define RESET_LOGIC_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1538))
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#define MEMORY_CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1544))
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#define MEMORY_MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1548))
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#define MEMORY_G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x154C))
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#define MEMORY_DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1550))
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#define MEMORY_CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1554))
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#define MEMORY_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1558))
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#define MEMORY_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x155C))
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#define MEMORY_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1560))
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#define MEMORY_ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1568))
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#define MEMORY_ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x156C))
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#define MEMORY_MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1570))
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#define MEMORY_DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1574))
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#define MEMORY_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1578))
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#define RESET_CMU_CAM0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1584))
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#define RESET_CMU_MSCL_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1588))
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#define RESET_CMU_G3D_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x158C))
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#define RESET_CMU_DISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1590))
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#define RESET_CMU_CAM1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1594))
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#define RESET_CMU_AUD_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x1598))
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#define RESET_CMU_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x159C))
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#define RESET_CMU_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15A0))
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#define RESET_CMU_ISP0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15A8))
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#define RESET_CMU_ISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15AC))
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#define RESET_CMU_MFC_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15B0))
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#define RESET_CMU_DISP1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15B4))
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#define RESET_CMU_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15B8))
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#define RESET_SLEEP_FSYS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15DC))
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#define RESET_SLEEP_BUS0_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15E0))
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#define RESET_SLEEP_FSYS1_SYS_PWR_REG ((void *)(PMU_ALIVE_BASE + 0x15F8))
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#define MNGS_CPU0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2000))
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#define MNGS_CPU0_STATUS ((void *)(PMU_ALIVE_BASE + 0x2004))
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#define MNGS_CPU0_OPTION ((void *)(PMU_ALIVE_BASE + 0x2008))
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#define MNGS_CPU0_RESET ((void *)(PMU_ALIVE_BASE + 0x200C))
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#define MNGS_CPU0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2010))
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#define MNGS_CPU0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2014))
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#define MNGS_CPU0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2018))
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#define MNGS_CPU0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x201C))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2020))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2024))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2028))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2030))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2034))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2038))
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#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x203C))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2040))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2044))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2048))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2050))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2054))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2058))
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#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x205C))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2060))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x2064))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x2068))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2070))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2074))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2078))
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#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x207C))
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#define MNGS_CPU1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2080))
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#define MNGS_CPU1_STATUS ((void *)(PMU_ALIVE_BASE + 0x2084))
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#define MNGS_CPU1_OPTION ((void *)(PMU_ALIVE_BASE + 0x2088))
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#define MNGS_CPU1_RESET ((void *)(PMU_ALIVE_BASE + 0x208C))
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#define MNGS_CPU1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2090))
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#define MNGS_CPU1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2094))
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#define MNGS_CPU1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2098))
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#define MNGS_CPU1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x209C))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x20A0))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x20A4))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x20A8))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x20B0))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x20B4))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x20B8))
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#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x20BC))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x20C0))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x20C4))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x20C8))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x20D0))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x20D4))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x20D8))
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#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x20DC))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x20E0))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x20E4))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x20E8))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x20F0))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x20F4))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x20F8))
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#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x20FC))
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#define MNGS_CPU2_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2100))
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#define MNGS_CPU2_STATUS ((void *)(PMU_ALIVE_BASE + 0x2104))
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#define MNGS_CPU2_OPTION ((void *)(PMU_ALIVE_BASE + 0x2108))
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#define MNGS_CPU2_RESET ((void *)(PMU_ALIVE_BASE + 0x210C))
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#define MNGS_CPU2_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2110))
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#define MNGS_CPU2_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2114))
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#define MNGS_CPU2_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2118))
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#define MNGS_CPU2_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x211C))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2120))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2124))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2128))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2130))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2134))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2138))
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#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x213C))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2140))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2144))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2148))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2150))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2154))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2158))
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#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x215C))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2160))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x2164))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x2168))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2170))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2174))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2178))
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#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x217C))
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#define MNGS_CPU3_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2180))
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#define MNGS_CPU3_STATUS ((void *)(PMU_ALIVE_BASE + 0x2184))
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#define MNGS_CPU3_OPTION ((void *)(PMU_ALIVE_BASE + 0x2188))
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#define MNGS_CPU3_RESET ((void *)(PMU_ALIVE_BASE + 0x218C))
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#define MNGS_CPU3_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2190))
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#define MNGS_CPU3_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2194))
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#define MNGS_CPU3_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2198))
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#define MNGS_CPU3_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x219C))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x21A0))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x21A4))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x21A8))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x21B0))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x21B4))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x21B8))
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#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x21BC))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x21C0))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x21C4))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x21C8))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x21D0))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x21D4))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x21D8))
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#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x21DC))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x21E0))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x21E4))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x21E8))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x21F0))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x21F4))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x21F8))
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#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x21FC))
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#define APOLLO_CPU0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2200))
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#define APOLLO_CPU0_STATUS ((void *)(PMU_ALIVE_BASE + 0x2204))
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#define APOLLO_CPU0_OPTION ((void *)(PMU_ALIVE_BASE + 0x2208))
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#define APOLLO_CPU0_RESET ((void *)(PMU_ALIVE_BASE + 0x220C))
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#define APOLLO_CPU0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2210))
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#define APOLLO_CPU0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2214))
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#define APOLLO_CPU0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2218))
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#define APOLLO_CPU0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x221C))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2220))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2224))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2228))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2230))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2234))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2238))
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#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x223C))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2240))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2244))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2248))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2250))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2254))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2258))
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#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x225C))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2260))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x2264))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x2268))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2270))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2274))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2278))
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#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x227C))
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#define APOLLO_CPU1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2280))
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#define APOLLO_CPU1_STATUS ((void *)(PMU_ALIVE_BASE + 0x2284))
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#define APOLLO_CPU1_OPTION ((void *)(PMU_ALIVE_BASE + 0x2288))
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#define APOLLO_CPU1_RESET ((void *)(PMU_ALIVE_BASE + 0x228C))
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#define APOLLO_CPU1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2290))
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#define APOLLO_CPU1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2294))
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#define APOLLO_CPU1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2298))
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#define APOLLO_CPU1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x229C))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x22A0))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x22A4))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x22A8))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x22B0))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x22B4))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x22B8))
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#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x22BC))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x22C0))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x22C4))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x22C8))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x22D0))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x22D4))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x22D8))
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#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x22DC))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x22E0))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x22E4))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x22E8))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x22F0))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x22F4))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x22F8))
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#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x22FC))
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#define APOLLO_CPU2_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2300))
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#define APOLLO_CPU2_STATUS ((void *)(PMU_ALIVE_BASE + 0x2304))
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#define APOLLO_CPU2_OPTION ((void *)(PMU_ALIVE_BASE + 0x2308))
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#define APOLLO_CPU2_RESET ((void *)(PMU_ALIVE_BASE + 0x230C))
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#define APOLLO_CPU2_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2310))
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#define APOLLO_CPU2_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2314))
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#define APOLLO_CPU2_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2318))
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#define APOLLO_CPU2_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x231C))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2320))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2324))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2328))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2330))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2334))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2338))
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#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x233C))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2340))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2344))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2348))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2350))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2354))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2358))
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#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x235C))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2360))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x2364))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x2368))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2370))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2374))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2378))
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#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x237C))
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#define APOLLO_CPU3_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2380))
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#define APOLLO_CPU3_STATUS ((void *)(PMU_ALIVE_BASE + 0x2384))
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#define APOLLO_CPU3_OPTION ((void *)(PMU_ALIVE_BASE + 0x2388))
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#define APOLLO_CPU3_RESET ((void *)(PMU_ALIVE_BASE + 0x238C))
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#define APOLLO_CPU3_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2390))
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#define APOLLO_CPU3_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2394))
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#define APOLLO_CPU3_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2398))
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#define APOLLO_CPU3_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x239C))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x23A0))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x23A4))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x23A8))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x23B0))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x23B4))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x23B8))
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#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x23BC))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x23C0))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x23C4))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x23C8))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x23D0))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x23D4))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x23D8))
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#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x23DC))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x23E0))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x23E4))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x23E8))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x23F0))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x23F4))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x23F8))
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#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x23FC))
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#define MNGS_NONCPU_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2400))
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#define MNGS_NONCPU_STATUS ((void *)(PMU_ALIVE_BASE + 0x2404))
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#define MNGS_NONCPU_OPTION ((void *)(PMU_ALIVE_BASE + 0x2408))
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#define MNGS_NONCPU_RESET ((void *)(PMU_ALIVE_BASE + 0x240C))
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#define MNGS_NONCPU_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2410))
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#define MNGS_NONCPU_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2414))
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#define MNGS_NONCPU_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2418))
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#define MNGS_NONCPU_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x241C))
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#define APOLLO_NONCPU_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2420))
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#define APOLLO_NONCPU_STATUS ((void *)(PMU_ALIVE_BASE + 0x2424))
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#define APOLLO_NONCPU_OPTION ((void *)(PMU_ALIVE_BASE + 0x2428))
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#define APOLLO_NONCPU_RESET ((void *)(PMU_ALIVE_BASE + 0x242C))
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#define APOLLO_NONCPU_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2430))
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#define APOLLO_NONCPU_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2434))
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#define APOLLO_NONCPU_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2438))
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#define APOLLO_NONCPU_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x243C))
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#define MNGS_DBG_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2440))
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#define MNGS_DBG_STATUS ((void *)(PMU_ALIVE_BASE + 0x2444))
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#define MNGS_DBG_OPTION ((void *)(PMU_ALIVE_BASE + 0x2448))
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#define MNGS_DBG_RESET ((void *)(PMU_ALIVE_BASE + 0x244C))
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#define MNGS_DBG_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2450))
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#define MNGS_DBG_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2454))
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#define MNGS_DBG_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2458))
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#define MNGS_DBG_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x245C))
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#define MNGS_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2480))
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#define MNGS_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x2484))
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#define MNGS_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x2488))
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#define MNGS_CPUSEQUENCER_RESET ((void *)(PMU_ALIVE_BASE + 0x248C))
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#define MNGS_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2490))
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#define MNGS_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2494))
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#define MNGS_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2498))
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#define MNGS_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x249C))
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#define APOLLO_CPUSEQUENCER_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x24A0))
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#define APOLLO_CPUSEQUENCER_STATUS ((void *)(PMU_ALIVE_BASE + 0x24A4))
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#define APOLLO_CPUSEQUENCER_OPTION ((void *)(PMU_ALIVE_BASE + 0x24A8))
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#define APOLLO_CPUSEQUENCER_RESET ((void *)(PMU_ALIVE_BASE + 0x24AC))
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#define APOLLO_CPUSEQUENCER_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x24B0))
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#define APOLLO_CPUSEQUENCER_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x24B4))
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#define APOLLO_CPUSEQUENCER_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x24B8))
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#define APOLLO_CPUSEQUENCER_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x24BC))
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#define CORTEXM3_APM_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2500))
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#define CORTEXM3_APM_STATUS ((void *)(PMU_ALIVE_BASE + 0x2504))
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#define CORTEXM3_APM_OPTION ((void *)(PMU_ALIVE_BASE + 0x2508))
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#define CORTEXM3_APM_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2510))
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#define CORTEXM3_APM_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2514))
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#define CORTEXM3_APM_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2518))
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#define CORTEXM3_APM_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x251C))
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#define A7IS_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2580))
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#define A7IS_STATUS ((void *)(PMU_ALIVE_BASE + 0x2584))
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#define A7IS_OPTION ((void *)(PMU_ALIVE_BASE + 0x2588))
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#define A7IS_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2590))
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#define A7IS_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2594))
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#define A7IS_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2598))
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#define A7IS_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x259C))
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#define DIS_IRQ_A7IS_LOCAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x25A0))
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#define DIS_IRQ_A7IS_LOCAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x25A4))
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#define DIS_IRQ_A7IS_LOCAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x25A8))
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#define DIS_IRQ_A7IS_LOCAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x25B0))
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#define DIS_IRQ_A7IS_LOCAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x25B4))
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#define DIS_IRQ_A7IS_LOCAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x25B8))
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#define DIS_IRQ_A7IS_LOCAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x25BC))
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#define DIS_IRQ_A7IS_CENTRAL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x25C0))
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#define DIS_IRQ_A7IS_CENTRAL_STATUS ((void *)(PMU_ALIVE_BASE + 0x25C4))
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#define DIS_IRQ_A7IS_CENTRAL_OPTION ((void *)(PMU_ALIVE_BASE + 0x25C8))
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#define DIS_IRQ_A7IS_CENTRAL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x25D0))
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#define DIS_IRQ_A7IS_CENTRAL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x25D4))
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#define DIS_IRQ_A7IS_CENTRAL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x25D8))
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#define DIS_IRQ_A7IS_CENTRAL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x25DC))
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#define MNGS_L2_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2600))
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#define MNGS_L2_STATUS ((void *)(PMU_ALIVE_BASE + 0x2604))
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#define MNGS_L2_OPTION ((void *)(PMU_ALIVE_BASE + 0x2608))
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#define MNGS_L2_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2610))
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#define MNGS_L2_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2614))
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#define MNGS_L2_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2618))
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#define MNGS_L2_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x261C))
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#define APOLLO_L2_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2620))
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#define APOLLO_L2_STATUS ((void *)(PMU_ALIVE_BASE + 0x2624))
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#define APOLLO_L2_OPTION ((void *)(PMU_ALIVE_BASE + 0x2628))
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#define APOLLO_L2_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2630))
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#define APOLLO_L2_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2634))
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#define APOLLO_L2_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2638))
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#define APOLLO_L2_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x263C))
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#define MNGS_L2_PWR_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2680))
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#define MNGS_L2_PWR_STATUS ((void *)(PMU_ALIVE_BASE + 0x2684))
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#define MNGS_L2_PWR_OPTION ((void *)(PMU_ALIVE_BASE + 0x2688))
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#define MNGS_L2_PWR_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2690))
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#define MNGS_L2_PWR_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2694))
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#define MNGS_L2_PWR_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2698))
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#define MNGS_L2_PWR_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x269C))
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#define CLKSTOP_CMU_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2800))
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#define CLKSTOP_CMU_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2804))
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#define CLKSTOP_CMU_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2808))
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#define CLKSTOP_CMU_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2810))
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#define CLKSTOP_CMU_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2814))
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#define CLKSTOP_CMU_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2818))
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#define CLKSTOP_CMU_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x281C))
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#define CLKRUN_CMU_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2820))
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#define CLKRUN_CMU_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2824))
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#define CLKRUN_CMU_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2828))
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#define CLKRUN_CMU_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2830))
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#define CLKRUN_CMU_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2834))
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#define CLKRUN_CMU_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2838))
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#define CLKRUN_CMU_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x283C))
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#define RETENTION_CMU_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2840))
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#define RETENTION_CMU_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2844))
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#define RETENTION_CMU_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2848))
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#define RETENTION_CMU_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2850))
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#define RETENTION_CMU_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2854))
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#define RETENTION_CMU_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2858))
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#define RETENTION_CMU_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x285C))
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#define RESET_CMU_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2860))
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#define RESET_CMU_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2864))
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#define RESET_CMU_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2868))
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#define RESET_CMU_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2870))
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#define RESET_CMU_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2874))
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#define RESET_CMU_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2878))
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#define RESET_CMU_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x287C))
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#define RESET_CPUCLKSTOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x28E0))
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#define RESET_CPUCLKSTOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x28E4))
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#define RESET_CPUCLKSTOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x28E8))
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#define RESET_CPUCLKSTOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x28F0))
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#define RESET_CPUCLKSTOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x28F4))
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#define RESET_CPUCLKSTOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x28F8))
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#define RESET_CPUCLKSTOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x28FC))
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#define CLKSTOP_CMU_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2900))
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#define CLKSTOP_CMU_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2904))
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#define CLKSTOP_CMU_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2908))
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#define CLKSTOP_CMU_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2910))
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#define CLKSTOP_CMU_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2914))
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#define CLKSTOP_CMU_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2918))
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#define CLKSTOP_CMU_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x291C))
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#define CLKRUN_CMU_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2920))
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#define CLKRUN_CMU_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2924))
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#define CLKRUN_CMU_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2928))
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#define CLKRUN_CMU_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2930))
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#define CLKRUN_CMU_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2934))
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#define CLKRUN_CMU_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2938))
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#define CLKRUN_CMU_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x293C))
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#define RETENTION_CMU_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2940))
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#define RETENTION_CMU_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2944))
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#define RETENTION_CMU_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2948))
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#define RETENTION_CMU_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2950))
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#define RETENTION_CMU_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2954))
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#define RETENTION_CMU_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2958))
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#define RETENTION_CMU_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x295C))
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#define RESET_CMU_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2960))
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#define RESET_CMU_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2964))
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#define RESET_CMU_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2968))
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#define RESET_CMU_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2970))
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#define RESET_CMU_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2974))
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#define RESET_CMU_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2978))
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#define RESET_CMU_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x297C))
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#define DDRPHY_CLKSTOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2980))
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#define DDRPHY_CLKSTOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2984))
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#define DDRPHY_CLKSTOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2988))
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#define DDRPHY_CLKSTOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2990))
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#define DDRPHY_CLKSTOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2994))
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#define DDRPHY_CLKSTOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2998))
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#define DDRPHY_CLKSTOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x299C))
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#define DDRPHY_ISO_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x29A0))
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#define DDRPHY_ISO_STATUS ((void *)(PMU_ALIVE_BASE + 0x29A4))
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#define DDRPHY_ISO_OPTION ((void *)(PMU_ALIVE_BASE + 0x29A8))
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#define DDRPHY_ISO_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x29B0))
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#define DDRPHY_ISO_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x29B4))
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#define DDRPHY_ISO_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x29B8))
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#define DDRPHY_ISO_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x29BC))
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#define DDRPHY_SOC2_ISO_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x29C0))
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#define DDRPHY_SOC2_ISO_STATUS ((void *)(PMU_ALIVE_BASE + 0x29C4))
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#define DDRPHY_SOC2_ISO_OPTION ((void *)(PMU_ALIVE_BASE + 0x29C8))
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#define DDRPHY_SOC2_ISO_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x29D0))
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#define DDRPHY_SOC2_ISO_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x29D4))
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#define DDRPHY_SOC2_ISO_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x29D8))
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#define DDRPHY_SOC2_ISO_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x29DC))
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#define DDRPHY_DLL_CLK_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x29E0))
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#define DDRPHY_DLL_CLK_STATUS ((void *)(PMU_ALIVE_BASE + 0x29E4))
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#define DDRPHY_DLL_CLK_OPTION ((void *)(PMU_ALIVE_BASE + 0x29E8))
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#define DDRPHY_DLL_CLK_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x29F0))
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#define DDRPHY_DLL_CLK_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x29F4))
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#define DDRPHY_DLL_CLK_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x29F8))
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#define DDRPHY_DLL_CLK_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x29FC))
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#define DISABLE_PLL_CMU_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2A00))
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#define DISABLE_PLL_CMU_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2A04))
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#define DISABLE_PLL_CMU_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2A08))
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#define DISABLE_PLL_CMU_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2A10))
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#define DISABLE_PLL_CMU_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2A14))
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#define DISABLE_PLL_CMU_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2A18))
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#define DISABLE_PLL_CMU_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2A1C))
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#define DISABLE_PLL_AUD_PLL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2A20))
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#define DISABLE_PLL_AUD_PLL_STATUS ((void *)(PMU_ALIVE_BASE + 0x2A24))
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#define DISABLE_PLL_AUD_PLL_OPTION ((void *)(PMU_ALIVE_BASE + 0x2A28))
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#define DISABLE_PLL_AUD_PLL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2A30))
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#define DISABLE_PLL_AUD_PLL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2A34))
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#define DISABLE_PLL_AUD_PLL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2A38))
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#define DISABLE_PLL_AUD_PLL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2A3C))
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#define DISABLE_PLL_CMU_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2B00))
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#define DISABLE_PLL_CMU_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2B04))
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#define DISABLE_PLL_CMU_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2B08))
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#define DISABLE_PLL_CMU_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2B10))
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#define DISABLE_PLL_CMU_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2B14))
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#define DISABLE_PLL_CMU_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2B18))
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#define DISABLE_PLL_CMU_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2B1C))
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#define RESET_AHEAD_CP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2B80))
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#define RESET_AHEAD_CP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2B84))
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#define RESET_AHEAD_CP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2B88))
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#define RESET_AHEAD_CP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2B90))
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#define RESET_AHEAD_CP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2B94))
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#define RESET_AHEAD_CP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2B98))
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#define RESET_AHEAD_CP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2B9C))
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#define TOP_BUS_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2C00))
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#define TOP_BUS_STATUS ((void *)(PMU_ALIVE_BASE + 0x2C04))
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#define TOP_BUS_OPTION ((void *)(PMU_ALIVE_BASE + 0x2C08))
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#define TOP_BUS_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2C10))
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#define TOP_BUS_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2C14))
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#define TOP_BUS_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2C18))
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#define TOP_BUS_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2C1C))
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#define TOP_RETENTION_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2C20))
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#define TOP_RETENTION_STATUS ((void *)(PMU_ALIVE_BASE + 0x2C24))
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#define TOP_RETENTION_OPTION ((void *)(PMU_ALIVE_BASE + 0x2C28))
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#define TOP_RETENTION_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2C30))
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#define TOP_RETENTION_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2C34))
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#define TOP_RETENTION_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2C38))
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#define TOP_RETENTION_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2C3C))
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#define TOP_PWR_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2C40))
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#define TOP_PWR_STATUS ((void *)(PMU_ALIVE_BASE + 0x2C44))
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#define TOP_PWR_OPTION ((void *)(PMU_ALIVE_BASE + 0x2C48))
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#define TOP_PWR_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2C50))
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#define TOP_PWR_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2C54))
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#define TOP_PWR_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2C58))
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#define TOP_PWR_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2C5C))
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#define CMU_PWR_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2C60))
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#define CMU_PWR_STATUS ((void *)(PMU_ALIVE_BASE + 0x2C60))
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#define CMU_PWR_OPTION ((void *)(PMU_ALIVE_BASE + 0x2C60))
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#define CMU_PWR_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2C60))
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#define CMU_PWR_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2C60))
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#define CMU_PWR_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2C60))
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#define CMU_PWR_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2C60))
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#define TOP_BUS_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2C80))
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#define TOP_BUS_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2C84))
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#define TOP_BUS_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2C88))
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#define TOP_BUS_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2C90))
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#define TOP_BUS_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2C94))
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#define TOP_BUS_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2C98))
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#define TOP_BUS_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2C9C))
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#define TOP_RETENTION_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2CA0))
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#define TOP_RETENTION_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2CA4))
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#define TOP_RETENTION_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2CA8))
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#define TOP_RETENTION_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2CB0))
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#define TOP_RETENTION_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2CB4))
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#define TOP_RETENTION_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2CB8))
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#define TOP_RETENTION_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2CBC))
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#define TOP_PWR_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2CC0))
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#define TOP_PWR_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2CC4))
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#define TOP_PWR_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2CC8))
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#define TOP_PWR_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2CD0))
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#define TOP_PWR_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2CD4))
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#define TOP_PWR_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2CD8))
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#define TOP_PWR_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2CDC))
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#define PSCDC_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2CE0))
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#define PSCDC_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2CE4))
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#define PSCDC_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2CE8))
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#define PSCDC_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2CF0))
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#define PSCDC_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2CF4))
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#define PSCDC_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2CF8))
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#define PSCDC_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2CFC))
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#define LOGIC_RESET_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2D00))
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#define LOGIC_RESET_STATUS ((void *)(PMU_ALIVE_BASE + 0x2D04))
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#define LOGIC_RESET_OPTION ((void *)(PMU_ALIVE_BASE + 0x2D08))
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#define LOGIC_RESET_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2D10))
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#define LOGIC_RESET_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2D14))
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#define LOGIC_RESET_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2D18))
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#define LOGIC_RESET_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2D1C))
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#define OSCCLK_GATE_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2D20))
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#define OSCCLK_GATE_STATUS ((void *)(PMU_ALIVE_BASE + 0x2D24))
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#define OSCCLK_GATE_OPTION ((void *)(PMU_ALIVE_BASE + 0x2D28))
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#define OSCCLK_GATE_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2D30))
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#define OSCCLK_GATE_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2D34))
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#define OSCCLK_GATE_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2D38))
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#define OSCCLK_GATE_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2D3C))
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#define SLEEP_RESET_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2D40))
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#define SLEEP_RESET_STATUS ((void *)(PMU_ALIVE_BASE + 0x2D44))
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#define SLEEP_RESET_OPTION ((void *)(PMU_ALIVE_BASE + 0x2D48))
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#define SLEEP_RESET_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2D50))
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#define SLEEP_RESET_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2D54))
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#define SLEEP_RESET_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2D58))
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#define SLEEP_RESET_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2D5C))
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#define LOGIC_RESET_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2D80))
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#define LOGIC_RESET_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2D84))
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#define LOGIC_RESET_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2D88))
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#define LOGIC_RESET_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2D90))
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#define LOGIC_RESET_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2D94))
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#define LOGIC_RESET_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2D98))
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#define LOGIC_RESET_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2D9C))
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#define OSCCLK_GATE_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2DA0))
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#define OSCCLK_GATE_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2DA4))
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#define OSCCLK_GATE_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2DA8))
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#define OSCCLK_GATE_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2DB0))
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#define OSCCLK_GATE_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2DB4))
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#define OSCCLK_GATE_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2DB8))
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#define OSCCLK_GATE_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2DBC))
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#define SLEEP_RESET_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2DC0))
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#define SLEEP_RESET_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2DC4))
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#define SLEEP_RESET_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2DC8))
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#define SLEEP_RESET_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2DD0))
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#define SLEEP_RESET_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2DD4))
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#define SLEEP_RESET_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2DD8))
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#define SLEEP_RESET_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2DDC))
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#define MEMORY_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2E00))
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#define MEMORY_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2E04))
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#define MEMORY_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2E08))
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#define MEMORY_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2E10))
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#define MEMORY_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2E14))
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#define MEMORY_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2E18))
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#define MEMORY_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2E1C))
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#define CLEANY_BUS_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2E60))
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#define CLEANY_BUS_STATUS ((void *)(PMU_ALIVE_BASE + 0x2E64))
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#define CLEANY_BUS_OPTION ((void *)(PMU_ALIVE_BASE + 0x2E68))
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#define CLEANY_BUS_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2E70))
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#define CLEANY_BUS_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2E74))
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#define CLEANY_BUS_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2E78))
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#define CLEANY_BUS_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2E7C))
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#define LOGIC_RESET_CP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2E80))
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#define LOGIC_RESET_CP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2E84))
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#define LOGIC_RESET_CP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2E88))
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#define LOGIC_RESET_CP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2E90))
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#define LOGIC_RESET_CP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2E94))
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#define LOGIC_RESET_CP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2E98))
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#define LOGIC_RESET_CP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2E9C))
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#define TCXO_GATE_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2EA0))
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#define TCXO_GATE_STATUS ((void *)(PMU_ALIVE_BASE + 0x2EA4))
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#define TCXO_GATE_OPTION ((void *)(PMU_ALIVE_BASE + 0x2EA8))
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#define TCXO_GATE_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2EB0))
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#define TCXO_GATE_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2EB4))
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#define TCXO_GATE_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2EB8))
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#define TCXO_GATE_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2EBC))
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#define RESET_ASB_CP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2EC0))
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#define RESET_ASB_CP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2EC4))
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#define RESET_ASB_CP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2EC8))
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#define RESET_ASB_CP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2ED0))
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#define RESET_ASB_CP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2ED4))
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#define RESET_ASB_CP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2ED8))
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#define RESET_ASB_CP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2EDC))
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#define RESET_ASB_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2EE0))
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#define RESET_ASB_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x2EE4))
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#define RESET_ASB_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x2EE8))
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#define RESET_ASB_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2EF0))
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#define RESET_ASB_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2EF4))
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#define RESET_ASB_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2EF8))
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#define RESET_ASB_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2EFC))
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#define MEMORY_IMEM_ALIVEIRAM_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2F00))
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#define MEMORY_IMEM_ALIVEIRAM_STATUS ((void *)(PMU_ALIVE_BASE + 0x2F04))
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#define MEMORY_IMEM_ALIVEIRAM_OPTION ((void *)(PMU_ALIVE_BASE + 0x2F08))
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#define MEMORY_IMEM_ALIVEIRAM_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2F10))
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#define MEMORY_IMEM_ALIVEIRAM_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2F14))
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#define MEMORY_IMEM_ALIVEIRAM_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2F18))
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#define MEMORY_IMEM_ALIVEIRAM_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2F1C))
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#define MEMORY_MIF_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2F20))
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#define MEMORY_MIF_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x2F24))
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#define MEMORY_MIF_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x2F28))
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#define MEMORY_MIF_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2F30))
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#define MEMORY_MIF_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2F34))
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#define MEMORY_MIF_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2F38))
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#define MEMORY_MIF_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2F3C))
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#define LOGIC_RESET_DDRPHY_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2F80))
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#define LOGIC_RESET_DDRPHY_STATUS ((void *)(PMU_ALIVE_BASE + 0x2F84))
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#define LOGIC_RESET_DDRPHY_OPTION ((void *)(PMU_ALIVE_BASE + 0x2F88))
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#define LOGIC_RESET_DDRPHY_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2F90))
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#define LOGIC_RESET_DDRPHY_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2F94))
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#define LOGIC_RESET_DDRPHY_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2F98))
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#define LOGIC_RESET_DDRPHY_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2F9C))
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#define RETENTION_DDRPHY_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2FA0))
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#define RETENTION_DDRPHY_STATUS ((void *)(PMU_ALIVE_BASE + 0x2FA4))
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#define RETENTION_DDRPHY_OPTION ((void *)(PMU_ALIVE_BASE + 0x2FA8))
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#define RETENTION_DDRPHY_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2FB0))
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#define RETENTION_DDRPHY_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2FB4))
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#define RETENTION_DDRPHY_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2FB8))
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#define RETENTION_DDRPHY_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2FBC))
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#define PWR_DDRPHY_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x2FE0))
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#define PWR_DDRPHY_STATUS ((void *)(PMU_ALIVE_BASE + 0x2FE4))
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#define PWR_DDRPHY_OPTION ((void *)(PMU_ALIVE_BASE + 0x2FE8))
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#define PWR_DDRPHY_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x2FF0))
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#define PWR_DDRPHY_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x2FF4))
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#define PWR_DDRPHY_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x2FF8))
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#define PWR_DDRPHY_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x2FFC))
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#define PAD_RETENTION_LPDDR4_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3000))
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#define PAD_RETENTION_LPDDR4_STATUS ((void *)(PMU_ALIVE_BASE + 0x3004))
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#define PAD_RETENTION_LPDDR4_OPTION ((void *)(PMU_ALIVE_BASE + 0x3008))
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#define PAD_RETENTION_LPDDR4_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3010))
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#define PAD_RETENTION_LPDDR4_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3014))
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#define PAD_RETENTION_LPDDR4_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3018))
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#define PAD_RETENTION_LPDDR4_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x301C))
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#define PAD_RETENTION_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3020))
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#define PAD_RETENTION_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x3024))
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#define PAD_RETENTION_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x3028))
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#define PAD_RETENTION_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3030))
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#define PAD_RETENTION_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3034))
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#define PAD_RETENTION_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3038))
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#define PAD_RETENTION_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x303C))
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#define PAD_RETENTION_JTAG_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3040))
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#define PAD_RETENTION_JTAG_STATUS ((void *)(PMU_ALIVE_BASE + 0x3044))
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#define PAD_RETENTION_JTAG_OPTION ((void *)(PMU_ALIVE_BASE + 0x3048))
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#define PAD_RETENTION_JTAG_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3050))
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#define PAD_RETENTION_JTAG_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3054))
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#define PAD_RETENTION_JTAG_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3058))
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#define PAD_RETENTION_JTAG_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x305C))
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#define PAD_RETENTION_PCIE_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3060))
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#define PAD_RETENTION_PCIE_STATUS ((void *)(PMU_ALIVE_BASE + 0x3064))
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#define PAD_RETENTION_PCIE_OPTION ((void *)(PMU_ALIVE_BASE + 0x3068))
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#define PAD_RETENTION_PCIE_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3070))
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#define PAD_RETENTION_PCIE_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3074))
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#define PAD_RETENTION_PCIE_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3078))
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#define PAD_RETENTION_PCIE_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x307C))
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#define PAD_RETENTION_UFS_CARD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3080))
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#define PAD_RETENTION_UFS_CARD_STATUS ((void *)(PMU_ALIVE_BASE + 0x3084))
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#define PAD_RETENTION_UFS_CARD_OPTION ((void *)(PMU_ALIVE_BASE + 0x3088))
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#define PAD_RETENTION_UFS_CARD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3090))
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#define PAD_RETENTION_UFS_CARD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3094))
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#define PAD_RETENTION_UFS_CARD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3098))
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#define PAD_RETENTION_UFS_CARD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x309C))
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#define PAD_RETENTION_MMC2_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x30C0))
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#define PAD_RETENTION_MMC2_STATUS ((void *)(PMU_ALIVE_BASE + 0x30C4))
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#define PAD_RETENTION_MMC2_OPTION ((void *)(PMU_ALIVE_BASE + 0x30C8))
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#define PAD_RETENTION_MMC2_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x30D0))
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#define PAD_RETENTION_MMC2_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x30D4))
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#define PAD_RETENTION_MMC2_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x30D8))
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#define PAD_RETENTION_MMC2_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x30DC))
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#define PAD_RETENTION_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3100))
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#define PAD_RETENTION_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x3104))
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#define PAD_RETENTION_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x3108))
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#define PAD_RETENTION_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3110))
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#define PAD_RETENTION_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3114))
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#define PAD_RETENTION_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3118))
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#define PAD_RETENTION_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x311C))
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#define PAD_RETENTION_UART_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3120))
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#define PAD_RETENTION_UART_STATUS ((void *)(PMU_ALIVE_BASE + 0x3124))
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#define PAD_RETENTION_UART_OPTION ((void *)(PMU_ALIVE_BASE + 0x3128))
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#define PAD_RETENTION_UART_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3130))
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#define PAD_RETENTION_UART_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3134))
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#define PAD_RETENTION_UART_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3138))
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#define PAD_RETENTION_UART_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x313C))
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#define PAD_RETENTION_MMC0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3140))
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#define PAD_RETENTION_MMC0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3144))
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#define PAD_RETENTION_MMC0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3148))
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#define PAD_RETENTION_MMC0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3150))
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#define PAD_RETENTION_MMC0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3154))
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#define PAD_RETENTION_MMC0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3158))
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#define PAD_RETENTION_MMC0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x315C))
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#define PAD_RETENTION_EBIA_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3180))
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#define PAD_RETENTION_EBIA_STATUS ((void *)(PMU_ALIVE_BASE + 0x3184))
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#define PAD_RETENTION_EBIA_OPTION ((void *)(PMU_ALIVE_BASE + 0x3188))
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#define PAD_RETENTION_EBIA_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3190))
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#define PAD_RETENTION_EBIA_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3194))
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#define PAD_RETENTION_EBIA_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3198))
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#define PAD_RETENTION_EBIA_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x319C))
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#define PAD_RETENTION_EBIB_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x31A0))
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#define PAD_RETENTION_EBIB_STATUS ((void *)(PMU_ALIVE_BASE + 0x31A4))
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#define PAD_RETENTION_EBIB_OPTION ((void *)(PMU_ALIVE_BASE + 0x31A8))
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#define PAD_RETENTION_EBIB_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x31B0))
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#define PAD_RETENTION_EBIB_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x31B4))
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#define PAD_RETENTION_EBIB_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x31B8))
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#define PAD_RETENTION_EBIB_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x31BC))
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#define PAD_RETENTION_SPI_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x31C0))
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#define PAD_RETENTION_SPI_STATUS ((void *)(PMU_ALIVE_BASE + 0x31C4))
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#define PAD_RETENTION_SPI_OPTION ((void *)(PMU_ALIVE_BASE + 0x31C8))
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#define PAD_RETENTION_SPI_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x31D0))
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#define PAD_RETENTION_SPI_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x31D4))
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#define PAD_RETENTION_SPI_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x31D8))
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#define PAD_RETENTION_SPI_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x31DC))
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#define PAD_RETENTION_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x31E0))
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#define PAD_RETENTION_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x31E4))
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#define PAD_RETENTION_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x31E8))
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#define PAD_RETENTION_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x31F0))
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#define PAD_RETENTION_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x31F4))
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#define PAD_RETENTION_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x31F8))
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#define PAD_RETENTION_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x31FC))
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#define PAD_ISOLATION_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3200))
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#define PAD_ISOLATION_STATUS ((void *)(PMU_ALIVE_BASE + 0x3204))
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#define PAD_ISOLATION_OPTION ((void *)(PMU_ALIVE_BASE + 0x3208))
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#define PAD_ISOLATION_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3210))
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#define PAD_ISOLATION_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3214))
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#define PAD_ISOLATION_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3218))
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#define PAD_ISOLATION_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x321C))
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#define PAD_RETENTION_BOOTLDO_0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3240))
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#define PAD_RETENTION_BOOTLDO_0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3244))
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#define PAD_RETENTION_BOOTLDO_0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3248))
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#define PAD_RETENTION_BOOTLDO_0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3250))
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#define PAD_RETENTION_BOOTLDO_0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3254))
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#define PAD_RETENTION_BOOTLDO_0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3258))
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#define PAD_RETENTION_BOOTLDO_0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x325C))
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#define PAD_RETENTION_UFS_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3260))
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#define PAD_RETENTION_UFS_STATUS ((void *)(PMU_ALIVE_BASE + 0x3264))
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#define PAD_RETENTION_UFS_OPTION ((void *)(PMU_ALIVE_BASE + 0x3268))
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#define PAD_RETENTION_UFS_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3270))
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#define PAD_RETENTION_UFS_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3274))
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#define PAD_RETENTION_UFS_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3278))
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#define PAD_RETENTION_UFS_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x327C))
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#define PAD_ISOLATION_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3280))
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#define PAD_ISOLATION_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x3284))
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#define PAD_ISOLATION_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x3288))
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#define PAD_ISOLATION_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3290))
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#define PAD_ISOLATION_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3294))
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#define PAD_ISOLATION_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3298))
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#define PAD_ISOLATION_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x329C))
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#define PAD_RETENTION_USB_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x32A0))
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#define PAD_RETENTION_USB_STATUS ((void *)(PMU_ALIVE_BASE + 0x32A4))
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#define PAD_RETENTION_USB_OPTION ((void *)(PMU_ALIVE_BASE + 0x32A8))
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#define PAD_RETENTION_USB_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x32B0))
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#define PAD_RETENTION_USB_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x32B4))
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#define PAD_RETENTION_USB_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x32B8))
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#define PAD_RETENTION_USB_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x32BC))
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#define PAD_RETENTION_BOOTLDO_1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x32C0))
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#define PAD_RETENTION_BOOTLDO_1_STATUS ((void *)(PMU_ALIVE_BASE + 0x32C4))
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#define PAD_RETENTION_BOOTLDO_1_OPTION ((void *)(PMU_ALIVE_BASE + 0x32C8))
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#define PAD_RETENTION_BOOTLDO_1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x32D0))
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#define PAD_RETENTION_BOOTLDO_1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x32D4))
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#define PAD_RETENTION_BOOTLDO_1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x32D8))
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#define PAD_RETENTION_BOOTLDO_1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x32DC))
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#define PAD_ALV_SEL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3300))
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#define PAD_ALV_SEL_STATUS ((void *)(PMU_ALIVE_BASE + 0x3304))
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#define PAD_ALV_SEL_OPTION0 ((void *)(PMU_ALIVE_BASE + 0x3308))
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#define PS_HOLD_CONTROL ((void *)(PMU_ALIVE_BASE + 0x330C))
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#define PAD_ALV_SEL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3310))
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#define PAD_ALV_SEL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3314))
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#define PAD_ALV_SEL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3318))
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#define PAD_ALV_SEL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x331C))
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#define XXTI_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3420))
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#define XXTI_STATUS ((void *)(PMU_ALIVE_BASE + 0x3424))
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#define XXTI_OPTION ((void *)(PMU_ALIVE_BASE + 0x3428))
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#define XXTI_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3430))
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#define XXTI_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3434))
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#define XXTI_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3438))
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#define XXTI_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x343C))
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#define TCXO_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3460))
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#define TCXO_STATUS ((void *)(PMU_ALIVE_BASE + 0x3464))
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#define TCXO_OPTION ((void *)(PMU_ALIVE_BASE + 0x3468))
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#define TCXO_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3470))
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#define TCXO_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3474))
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#define TCXO_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3478))
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#define TCXO_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x347C))
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#define EXT_REGULATOR_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3600))
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#define EXT_REGULATOR_STATUS ((void *)(PMU_ALIVE_BASE + 0x3604))
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#define EXT_REGULATOR_OPTION ((void *)(PMU_ALIVE_BASE + 0x3608))
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#define EXT_REGULATOR_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3610))
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#define EXT_REGULATOR_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3614))
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#define EXT_REGULATOR_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3618))
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#define EXT_REGULATOR_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x361C))
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#define EXT_REGULATOR_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3620))
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#define EXT_REGULATOR_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x3624))
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#define EXT_REGULATOR_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x3628))
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#define EXT_REGULATOR_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3630))
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#define EXT_REGULATOR_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3634))
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#define EXT_REGULATOR_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3638))
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#define EXT_REGULATOR_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x363C))
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#define GPIO_MODE_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3800))
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#define GPIO_MODE_STATUS ((void *)(PMU_ALIVE_BASE + 0x3804))
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#define GPIO_MODE_OPTION ((void *)(PMU_ALIVE_BASE + 0x3808))
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#define GPIO_MODE_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3810))
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#define GPIO_MODE_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3814))
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#define GPIO_MODE_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3818))
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#define GPIO_MODE_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x381C))
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#define GPIO_MODE_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3820))
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#define GPIO_MODE_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3824))
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#define GPIO_MODE_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3828))
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#define GPIO_MODE_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3830))
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#define GPIO_MODE_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3834))
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#define GPIO_MODE_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3838))
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#define GPIO_MODE_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x383C))
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#define GPIO_MODE_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3840))
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#define GPIO_MODE_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x3844))
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#define GPIO_MODE_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x3848))
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#define GPIO_MODE_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3850))
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#define GPIO_MODE_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3854))
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#define GPIO_MODE_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3858))
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#define GPIO_MODE_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x385C))
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#define GPIO_MODE_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3900))
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#define GPIO_MODE_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x3904))
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#define GPIO_MODE_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x3908))
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#define GPIO_MODE_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3910))
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#define GPIO_MODE_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3914))
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#define GPIO_MODE_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3918))
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#define GPIO_MODE_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x391C))
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#define GPIO_MODE_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x39E0))
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#define GPIO_MODE_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x39E4))
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#define GPIO_MODE_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x39E8))
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#define GPIO_MODE_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x39F0))
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#define GPIO_MODE_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x39F4))
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#define GPIO_MODE_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x39F8))
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#define GPIO_MODE_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x39FC))
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#define CLKSTOP_OPEN_CMU_TOP_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3C00))
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#define CLKSTOP_OPEN_CMU_TOP_STATUS ((void *)(PMU_ALIVE_BASE + 0x3C04))
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#define CLKSTOP_OPEN_CMU_TOP_OPTION ((void *)(PMU_ALIVE_BASE + 0x3C08))
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#define CLKSTOP_OPEN_CMU_TOP_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3C10))
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#define CLKSTOP_OPEN_CMU_TOP_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3C14))
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#define CLKSTOP_OPEN_CMU_TOP_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3C18))
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#define CLKSTOP_OPEN_CMU_TOP_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3C1C))
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#define CLKSTOP_OPEN_CMU_MIF_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3C20))
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#define CLKSTOP_OPEN_CMU_MIF_STATUS ((void *)(PMU_ALIVE_BASE + 0x3C24))
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#define CLKSTOP_OPEN_CMU_MIF_OPTION ((void *)(PMU_ALIVE_BASE + 0x3C28))
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#define CLKSTOP_OPEN_CMU_MIF_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3C30))
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#define CLKSTOP_OPEN_CMU_MIF_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3C34))
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#define CLKSTOP_OPEN_CMU_MIF_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3C38))
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#define CLKSTOP_OPEN_CMU_MIF_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3C3C))
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#define CLKSTOP_OPEN_CMU_CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3C40))
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#define CLKSTOP_OPEN_CMU_CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3C44))
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#define CLKSTOP_OPEN_CMU_CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3C48))
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#define CLKSTOP_OPEN_CMU_CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3C50))
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#define CLKSTOP_OPEN_CMU_CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3C54))
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#define CLKSTOP_OPEN_CMU_CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3C58))
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#define CLKSTOP_OPEN_CMU_CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3C5C))
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#define CLKSTOP_OPEN_CMU_MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3C60))
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#define CLKSTOP_OPEN_CMU_MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x3C64))
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#define CLKSTOP_OPEN_CMU_MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x3C68))
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#define CLKSTOP_OPEN_CMU_MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3C70))
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#define CLKSTOP_OPEN_CMU_MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3C74))
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#define CLKSTOP_OPEN_CMU_MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3C78))
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#define CLKSTOP_OPEN_CMU_MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3C7C))
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#define CLKSTOP_OPEN_CMU_G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3C80))
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#define CLKSTOP_OPEN_CMU_G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x3C84))
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#define CLKSTOP_OPEN_CMU_G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x3C88))
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#define CLKSTOP_OPEN_CMU_G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3C90))
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#define CLKSTOP_OPEN_CMU_G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3C94))
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#define CLKSTOP_OPEN_CMU_G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3C98))
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#define CLKSTOP_OPEN_CMU_G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3C9C))
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#define CLKSTOP_OPEN_CMU_DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3CA0))
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#define CLKSTOP_OPEN_CMU_DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3CA4))
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#define CLKSTOP_OPEN_CMU_DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3CA8))
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#define CLKSTOP_OPEN_CMU_DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3CB0))
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#define CLKSTOP_OPEN_CMU_DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3CB4))
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#define CLKSTOP_OPEN_CMU_DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3CB8))
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#define CLKSTOP_OPEN_CMU_DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3CBC))
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#define CLKSTOP_OPEN_CMU_CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3CC0))
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#define CLKSTOP_OPEN_CMU_CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x3CC4))
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#define CLKSTOP_OPEN_CMU_CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x3CC8))
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#define CLKSTOP_OPEN_CMU_CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3CD0))
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#define CLKSTOP_OPEN_CMU_CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3CD4))
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#define CLKSTOP_OPEN_CMU_CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3CD8))
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#define CLKSTOP_OPEN_CMU_CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3CDC))
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#define CLKSTOP_OPEN_CMU_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3CE0))
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#define CLKSTOP_OPEN_CMU_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x3CE4))
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#define CLKSTOP_OPEN_CMU_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x3CE8))
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#define CLKSTOP_OPEN_CMU_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3CF0))
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#define CLKSTOP_OPEN_CMU_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3CF4))
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#define CLKSTOP_OPEN_CMU_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3CF8))
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#define CLKSTOP_OPEN_CMU_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3CFC))
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#define CLKSTOP_OPEN_CMU_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3D00))
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#define CLKSTOP_OPEN_CMU_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3D04))
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#define CLKSTOP_OPEN_CMU_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3D08))
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#define CLKSTOP_OPEN_CMU_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3D10))
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#define CLKSTOP_OPEN_CMU_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3D14))
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#define CLKSTOP_OPEN_CMU_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3D18))
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#define CLKSTOP_OPEN_CMU_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3D1C))
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#define CLKSTOP_OPEN_CMU_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3D20))
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#define CLKSTOP_OPEN_CMU_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3D24))
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#define CLKSTOP_OPEN_CMU_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3D28))
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#define CLKSTOP_OPEN_CMU_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3D30))
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#define CLKSTOP_OPEN_CMU_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3D34))
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#define CLKSTOP_OPEN_CMU_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3D38))
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#define CLKSTOP_OPEN_CMU_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3D3C))
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#define CLKSTOP_OPEN_CMU_ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3D40))
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#define CLKSTOP_OPEN_CMU_ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x3D44))
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#define CLKSTOP_OPEN_CMU_ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x3D48))
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#define CLKSTOP_OPEN_CMU_ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3D50))
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#define CLKSTOP_OPEN_CMU_ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3D54))
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#define CLKSTOP_OPEN_CMU_ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3D58))
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#define CLKSTOP_OPEN_CMU_ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3D5C))
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#define CLKSTOP_OPEN_CMU_ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3D60))
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#define CLKSTOP_OPEN_CMU_ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x3D64))
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#define CLKSTOP_OPEN_CMU_ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x3D68))
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#define CLKSTOP_OPEN_CMU_ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3D70))
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#define CLKSTOP_OPEN_CMU_ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3D74))
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#define CLKSTOP_OPEN_CMU_ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3D78))
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#define CLKSTOP_OPEN_CMU_ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3D7C))
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#define CLKSTOP_OPEN_CMU_MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3D80))
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#define CLKSTOP_OPEN_CMU_MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x3D84))
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#define CLKSTOP_OPEN_CMU_MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x3D88))
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#define CLKSTOP_OPEN_CMU_MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3D90))
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#define CLKSTOP_OPEN_CMU_MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3D94))
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#define CLKSTOP_OPEN_CMU_MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3D98))
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#define CLKSTOP_OPEN_CMU_MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3D9C))
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#define CLKSTOP_OPEN_CMU_DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3DA0))
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#define CLKSTOP_OPEN_CMU_DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x3DA4))
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#define CLKSTOP_OPEN_CMU_DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x3DA8))
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#define CLKSTOP_OPEN_CMU_DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3DB0))
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#define CLKSTOP_OPEN_CMU_DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3DB4))
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#define CLKSTOP_OPEN_CMU_DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3DB8))
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#define CLKSTOP_OPEN_CMU_DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3DBC))
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#define CLKSTOP_OPEN_CMU_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x3DC0))
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#define CLKSTOP_OPEN_CMU_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x3DC4))
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#define CLKSTOP_OPEN_CMU_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x3DC8))
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#define CLKSTOP_OPEN_CMU_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x3DD0))
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#define CLKSTOP_OPEN_CMU_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x3DD4))
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#define CLKSTOP_OPEN_CMU_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x3DD8))
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#define CLKSTOP_OPEN_CMU_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x3DDC))
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#define CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4020))
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#define CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4024))
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#define CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4028))
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#define CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4030))
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#define CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4034))
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#define CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4038))
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#define CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x403C))
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#define MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4040))
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#define MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x4044))
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#define MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x4048))
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#define MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4050))
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#define MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4054))
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#define MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4058))
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#define MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x405C))
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#define G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4060))
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#define G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x4064))
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#define G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x4068))
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#define G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4070))
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#define G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4074))
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#define G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4078))
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#define G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x407C))
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#define DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4080))
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#define DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4084))
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#define DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4088))
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#define DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4090))
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#define DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4094))
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#define DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4098))
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#define DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x409C))
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#define CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x40A0))
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#define CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x40A4))
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#define CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x40A8))
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#define CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x40B0))
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#define CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x40B4))
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#define CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x40B8))
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#define CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x40BC))
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#define AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x40C0))
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#define AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x40C4))
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#define AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x40C8))
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#define AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x40D0))
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#define AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x40D4))
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#define AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x40D8))
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#define AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x40DC))
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#define FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x40E0))
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#define FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x40E4))
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#define FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x40E8))
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#define FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x40F0))
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#define FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x40F4))
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#define FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x40F8))
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#define FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x40FC))
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#define BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4100))
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#define BUS0_STATUS_ ((void *)(PMU_ALIVE_BASE + 0x4104)) //BJ : because of duplicated definition, i added "_".
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#define BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4108))
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#define BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4110))
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#define BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4114))
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#define BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4118))
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#define BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x411C))
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#define ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4140))
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#define ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4144))
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#define ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4148))
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#define ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4150))
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#define ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4154))
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#define ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4158))
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#define ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x415C))
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#define ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4160))
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#define ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4164))
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#define ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4168))
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#define ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4170))
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#define ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4174))
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#define ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4178))
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#define ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x417C))
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#define MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4180))
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#define MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x4184))
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#define MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x4188))
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#define MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4190))
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#define MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4194))
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#define MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4198))
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#define MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x419C))
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#define DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x41A0))
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#define DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x41A4))
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#define DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x41A8))
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#define DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x41B0))
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#define DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x41B4))
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#define DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x41B8))
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#define DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x41BC))
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#define FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x41C0))
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#define FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x41C4))
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#define FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x41C8))
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#define FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x41D0))
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#define FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x41D4))
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#define FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x41D8))
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#define FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x41DC))
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#define CLKRUN_CMU_CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4220))
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#define CLKRUN_CMU_CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4224))
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#define CLKRUN_CMU_CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4228))
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#define CLKRUN_CMU_CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4230))
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#define CLKRUN_CMU_CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4234))
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#define CLKRUN_CMU_CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4238))
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#define CLKRUN_CMU_CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x423C))
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#define CLKRUN_CMU_MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4240))
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#define CLKRUN_CMU_MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x4244))
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#define CLKRUN_CMU_MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x4248))
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#define CLKRUN_CMU_MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4250))
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#define CLKRUN_CMU_MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4254))
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#define CLKRUN_CMU_MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4258))
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#define CLKRUN_CMU_MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x425C))
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#define CLKRUN_CMU_G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4260))
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#define CLKRUN_CMU_G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x4264))
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#define CLKRUN_CMU_G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x4268))
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#define CLKRUN_CMU_G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4270))
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#define CLKRUN_CMU_G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4274))
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#define CLKRUN_CMU_G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4278))
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#define CLKRUN_CMU_G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x427C))
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#define CLKRUN_CMU_DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4280))
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#define CLKRUN_CMU_DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4284))
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#define CLKRUN_CMU_DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4288))
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#define CLKRUN_CMU_DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4290))
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#define CLKRUN_CMU_DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4294))
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#define CLKRUN_CMU_DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4298))
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#define CLKRUN_CMU_DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x429C))
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#define CLKRUN_CMU_CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x42A0))
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#define CLKRUN_CMU_CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x42A4))
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#define CLKRUN_CMU_CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x42A8))
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#define CLKRUN_CMU_CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x42B0))
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#define CLKRUN_CMU_CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x42B4))
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#define CLKRUN_CMU_CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x42B8))
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#define CLKRUN_CMU_CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x42BC))
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#define CLKRUN_CMU_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x42C0))
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#define CLKRUN_CMU_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x42C4))
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#define CLKRUN_CMU_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x42C8))
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#define CLKRUN_CMU_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x42D0))
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#define CLKRUN_CMU_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x42D4))
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#define CLKRUN_CMU_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x42D8))
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#define CLKRUN_CMU_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x42DC))
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#define CLKRUN_CMU_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x42E0))
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#define CLKRUN_CMU_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x42E4))
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#define CLKRUN_CMU_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x42E8))
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#define CLKRUN_CMU_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x42F0))
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#define CLKRUN_CMU_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x42F4))
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#define CLKRUN_CMU_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x42F8))
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#define CLKRUN_CMU_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x42FC))
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#define CLKRUN_CMU_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4300))
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#define CLKRUN_CMU_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4304))
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#define CLKRUN_CMU_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4308))
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#define CLKRUN_CMU_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4310))
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#define CLKRUN_CMU_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4314))
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#define CLKRUN_CMU_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4318))
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#define CLKRUN_CMU_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x431C))
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#define CLKRUN_CMU_ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4340))
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#define CLKRUN_CMU_ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4344))
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#define CLKRUN_CMU_ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4348))
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#define CLKRUN_CMU_ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4350))
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#define CLKRUN_CMU_ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4354))
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#define CLKRUN_CMU_ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4358))
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#define CLKRUN_CMU_ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x435C))
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#define CLKRUN_CMU_ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4360))
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#define CLKRUN_CMU_ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4364))
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#define CLKRUN_CMU_ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4368))
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#define CLKRUN_CMU_ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4370))
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#define CLKRUN_CMU_ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4374))
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#define CLKRUN_CMU_ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4378))
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#define CLKRUN_CMU_ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x437C))
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#define CLKRUN_CMU_MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4380))
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#define CLKRUN_CMU_MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x4384))
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#define CLKRUN_CMU_MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x4388))
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#define CLKRUN_CMU_MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4390))
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#define CLKRUN_CMU_MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4394))
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#define CLKRUN_CMU_MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4398))
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#define CLKRUN_CMU_MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x439C))
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#define CLKRUN_CMU_DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x43A0))
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#define CLKRUN_CMU_DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x43A4))
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#define CLKRUN_CMU_DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x43A8))
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#define CLKRUN_CMU_DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x43B0))
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#define CLKRUN_CMU_DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x43B4))
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#define CLKRUN_CMU_DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x43B8))
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#define CLKRUN_CMU_DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x43BC))
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#define CLKRUN_CMU_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x43C0))
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#define CLKRUN_CMU_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x43C4))
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#define CLKRUN_CMU_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x43C8))
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#define CLKRUN_CMU_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x43D0))
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#define CLKRUN_CMU_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x43D4))
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#define CLKRUN_CMU_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x43D8))
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#define CLKRUN_CMU_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x43DC))
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#define CLKSTOP_CMU_CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4420))
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#define CLKSTOP_CMU_CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4424))
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#define CLKSTOP_CMU_CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4428))
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#define CLKSTOP_CMU_CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4430))
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#define CLKSTOP_CMU_CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4434))
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#define CLKSTOP_CMU_CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4438))
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#define CLKSTOP_CMU_CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x443C))
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#define CLKSTOP_CMU_MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4440))
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#define CLKSTOP_CMU_MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x4444))
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#define CLKSTOP_CMU_MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x4448))
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#define CLKSTOP_CMU_MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4450))
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#define CLKSTOP_CMU_MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4454))
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#define CLKSTOP_CMU_MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4458))
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#define CLKSTOP_CMU_MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x445C))
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#define CLKSTOP_CMU_G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4460))
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#define CLKSTOP_CMU_G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x4464))
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#define CLKSTOP_CMU_G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x4468))
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#define CLKSTOP_CMU_G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4470))
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#define CLKSTOP_CMU_G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4474))
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#define CLKSTOP_CMU_G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4478))
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#define CLKSTOP_CMU_G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x447C))
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#define CLKSTOP_CMU_DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4480))
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#define CLKSTOP_CMU_DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4484))
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#define CLKSTOP_CMU_DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4488))
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#define CLKSTOP_CMU_DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4490))
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#define CLKSTOP_CMU_DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4494))
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#define CLKSTOP_CMU_DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4498))
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#define CLKSTOP_CMU_DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x449C))
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#define CLKSTOP_CMU_CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x44A0))
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#define CLKSTOP_CMU_CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x44A4))
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#define CLKSTOP_CMU_CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x44A8))
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#define CLKSTOP_CMU_CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x44B0))
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#define CLKSTOP_CMU_CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x44B4))
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#define CLKSTOP_CMU_CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x44B8))
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#define CLKSTOP_CMU_CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x44BC))
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#define CLKSTOP_CMU_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x44C0))
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#define CLKSTOP_CMU_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x44C4))
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#define CLKSTOP_CMU_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x44C8))
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#define CLKSTOP_CMU_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x44D0))
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#define CLKSTOP_CMU_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x44D4))
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#define CLKSTOP_CMU_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x44D8))
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#define CLKSTOP_CMU_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x44DC))
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#define CLKSTOP_CMU_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x44E0))
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#define CLKSTOP_CMU_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x44E4))
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#define CLKSTOP_CMU_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x44E8))
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#define CLKSTOP_CMU_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x44F0))
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#define CLKSTOP_CMU_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x44F4))
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#define CLKSTOP_CMU_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x44F8))
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#define CLKSTOP_CMU_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x44FC))
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#define CLKSTOP_CMU_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4500))
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#define CLKSTOP_CMU_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4504))
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#define CLKSTOP_CMU_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4508))
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#define CLKSTOP_CMU_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4510))
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#define CLKSTOP_CMU_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4514))
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#define CLKSTOP_CMU_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4518))
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#define CLKSTOP_CMU_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x451C))
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#define CLKSTOP_CMU_ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4540))
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#define CLKSTOP_CMU_ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4544))
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#define CLKSTOP_CMU_ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4548))
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#define CLKSTOP_CMU_ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4550))
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#define CLKSTOP_CMU_ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4554))
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#define CLKSTOP_CMU_ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4558))
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#define CLKSTOP_CMU_ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x455C))
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#define CLKSTOP_CMU_ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4560))
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#define CLKSTOP_CMU_ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4564))
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#define CLKSTOP_CMU_ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4568))
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#define CLKSTOP_CMU_ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4570))
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#define CLKSTOP_CMU_ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4574))
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#define CLKSTOP_CMU_ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4578))
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#define CLKSTOP_CMU_ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x457C))
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#define CLKSTOP_CMU_MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4580))
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#define CLKSTOP_CMU_MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x4584))
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#define CLKSTOP_CMU_MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x4588))
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#define CLKSTOP_CMU_MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4590))
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#define CLKSTOP_CMU_MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4594))
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#define CLKSTOP_CMU_MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4598))
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#define CLKSTOP_CMU_MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x459C))
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#define CLKSTOP_CMU_DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x45A0))
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#define CLKSTOP_CMU_DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x45A4))
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#define CLKSTOP_CMU_DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x45A8))
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#define CLKSTOP_CMU_DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x45B0))
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#define CLKSTOP_CMU_DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x45B4))
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#define CLKSTOP_CMU_DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x45B8))
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#define CLKSTOP_CMU_DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x45BC))
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#define CLKSTOP_CMU_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x45C0))
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#define CLKSTOP_CMU_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x45C4))
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#define CLKSTOP_CMU_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x45C8))
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#define CLKSTOP_CMU_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x45D0))
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#define CLKSTOP_CMU_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x45D4))
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#define CLKSTOP_CMU_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x45D8))
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#define CLKSTOP_CMU_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x45DC))
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#define DISABLE_PLL_CMU_CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4620))
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#define DISABLE_PLL_CMU_CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4624))
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#define DISABLE_PLL_CMU_CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4628))
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#define DISABLE_PLL_CMU_CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4630))
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#define DISABLE_PLL_CMU_CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4634))
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#define DISABLE_PLL_CMU_CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4638))
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#define DISABLE_PLL_CMU_CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x463C))
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#define DISABLE_PLL_CMU_MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4640))
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#define DISABLE_PLL_CMU_MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x4644))
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#define DISABLE_PLL_CMU_MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x4648))
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#define DISABLE_PLL_CMU_MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4650))
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#define DISABLE_PLL_CMU_MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4654))
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#define DISABLE_PLL_CMU_MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4658))
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#define DISABLE_PLL_CMU_MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x465C))
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#define DISABLE_PLL_CMU_G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4660))
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#define DISABLE_PLL_CMU_G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x4664))
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#define DISABLE_PLL_CMU_G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x4668))
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#define DISABLE_PLL_CMU_G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4670))
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#define DISABLE_PLL_CMU_G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4674))
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#define DISABLE_PLL_CMU_G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4678))
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#define DISABLE_PLL_CMU_G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x467C))
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#define DISABLE_PLL_CMU_DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4680))
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#define DISABLE_PLL_CMU_DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4684))
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#define DISABLE_PLL_CMU_DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4688))
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#define DISABLE_PLL_CMU_DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4690))
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#define DISABLE_PLL_CMU_DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4694))
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#define DISABLE_PLL_CMU_DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4698))
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#define DISABLE_PLL_CMU_DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x469C))
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#define DISABLE_PLL_CMU_CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x46A0))
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#define DISABLE_PLL_CMU_CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x46A4))
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#define DISABLE_PLL_CMU_CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x46A8))
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#define DISABLE_PLL_CMU_CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x46B0))
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#define DISABLE_PLL_CMU_CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x46B4))
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#define DISABLE_PLL_CMU_CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x46B8))
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#define DISABLE_PLL_CMU_CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x46BC))
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#define DISABLE_PLL_CMU_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x46C0))
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#define DISABLE_PLL_CMU_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x46C4))
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#define DISABLE_PLL_CMU_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x46C8))
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#define DISABLE_PLL_CMU_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x46D0))
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#define DISABLE_PLL_CMU_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x46D4))
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#define DISABLE_PLL_CMU_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x46D8))
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#define DISABLE_PLL_CMU_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x46DC))
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#define DISABLE_PLL_CMU_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x46E0))
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#define DISABLE_PLL_CMU_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x46E4))
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#define DISABLE_PLL_CMU_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x46E8))
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#define DISABLE_PLL_CMU_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x46F0))
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#define DISABLE_PLL_CMU_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x46F4))
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#define DISABLE_PLL_CMU_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x46F8))
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#define DISABLE_PLL_CMU_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x46FC))
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#define DISABLE_PLL_CMU_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4700))
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#define DISABLE_PLL_CMU_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4704))
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#define DISABLE_PLL_CMU_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4708))
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#define DISABLE_PLL_CMU_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4710))
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#define DISABLE_PLL_CMU_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4714))
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#define DISABLE_PLL_CMU_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4718))
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#define DISABLE_PLL_CMU_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x471C))
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#define DISABLE_PLL_CMU_ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4740))
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#define DISABLE_PLL_CMU_ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4744))
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#define DISABLE_PLL_CMU_ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4748))
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#define DISABLE_PLL_CMU_ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4750))
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#define DISABLE_PLL_CMU_ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4754))
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#define DISABLE_PLL_CMU_ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4758))
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#define DISABLE_PLL_CMU_ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x475C))
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#define DISABLE_PLL_CMU_ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4760))
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#define DISABLE_PLL_CMU_ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4764))
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#define DISABLE_PLL_CMU_ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4768))
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#define DISABLE_PLL_CMU_ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4770))
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#define DISABLE_PLL_CMU_ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4774))
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#define DISABLE_PLL_CMU_ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4778))
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#define DISABLE_PLL_CMU_ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x477C))
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#define DISABLE_PLL_CMU_MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4780))
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#define DISABLE_PLL_CMU_MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x4784))
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#define DISABLE_PLL_CMU_MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x4788))
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#define DISABLE_PLL_CMU_MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4790))
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#define DISABLE_PLL_CMU_MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4794))
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#define DISABLE_PLL_CMU_MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4798))
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#define DISABLE_PLL_CMU_MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x479C))
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#define DISABLE_PLL_CMU_DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x47A0))
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#define DISABLE_PLL_CMU_DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x47A4))
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#define DISABLE_PLL_CMU_DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x47A8))
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#define DISABLE_PLL_CMU_DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x47B0))
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#define DISABLE_PLL_CMU_DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x47B4))
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#define DISABLE_PLL_CMU_DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x47B8))
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#define DISABLE_PLL_CMU_DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x47BC))
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#define DISABLE_PLL_CMU_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x47C0))
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#define DISABLE_PLL_CMU_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x47C4))
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#define DISABLE_PLL_CMU_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x47C8))
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#define DISABLE_PLL_CMU_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x47D0))
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#define DISABLE_PLL_CMU_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x47D4))
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#define DISABLE_PLL_CMU_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x47D8))
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#define DISABLE_PLL_CMU_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x47DC))
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#define RESET_LOGIC_CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4820))
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#define RESET_LOGIC_CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4824))
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#define RESET_LOGIC_CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4828))
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#define RESET_LOGIC_CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4830))
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#define RESET_LOGIC_CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4834))
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#define RESET_LOGIC_CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4838))
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#define RESET_LOGIC_CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x483C))
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#define RESET_LOGIC_MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4840))
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#define RESET_LOGIC_MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x4844))
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#define RESET_LOGIC_MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x4848))
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#define RESET_LOGIC_MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4850))
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#define RESET_LOGIC_MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4854))
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#define RESET_LOGIC_MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4858))
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#define RESET_LOGIC_MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x485C))
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#define RESET_LOGIC_G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4860))
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#define RESET_LOGIC_G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x4864))
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#define RESET_LOGIC_G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x4868))
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#define RESET_LOGIC_G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4870))
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#define RESET_LOGIC_G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4874))
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#define RESET_LOGIC_G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4878))
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#define RESET_LOGIC_G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x487C))
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#define RESET_LOGIC_DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4880))
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#define RESET_LOGIC_DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4884))
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#define RESET_LOGIC_DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4888))
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#define RESET_LOGIC_DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4890))
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#define RESET_LOGIC_DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4894))
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#define RESET_LOGIC_DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4898))
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#define RESET_LOGIC_DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x489C))
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#define RESET_LOGIC_CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x48A0))
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#define RESET_LOGIC_CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x48A4))
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#define RESET_LOGIC_CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x48A8))
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#define RESET_LOGIC_CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x48B0))
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#define RESET_LOGIC_CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x48B4))
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#define RESET_LOGIC_CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x48B8))
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#define RESET_LOGIC_CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x48BC))
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#define RESET_LOGIC_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x48C0))
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#define RESET_LOGIC_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x48C4))
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#define RESET_LOGIC_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x48C8))
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#define RESET_LOGIC_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x48D0))
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#define RESET_LOGIC_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x48D4))
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#define RESET_LOGIC_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x48D8))
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#define RESET_LOGIC_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x48DC))
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#define RESET_LOGIC_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x48E0))
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#define RESET_LOGIC_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x48E4))
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#define RESET_LOGIC_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x48E8))
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#define RESET_LOGIC_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x48F0))
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#define RESET_LOGIC_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x48F4))
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#define RESET_LOGIC_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x48F8))
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#define RESET_LOGIC_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x48FC))
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#define RESET_LOGIC_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4900))
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#define RESET_LOGIC_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4904))
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#define RESET_LOGIC_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4908))
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#define RESET_LOGIC_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4910))
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#define RESET_LOGIC_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4914))
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#define RESET_LOGIC_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4918))
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#define RESET_LOGIC_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x491C))
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#define RESET_LOGIC_ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4940))
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#define RESET_LOGIC_ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4944))
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#define RESET_LOGIC_ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4948))
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#define RESET_LOGIC_ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4950))
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#define RESET_LOGIC_ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4954))
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#define RESET_LOGIC_ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4958))
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#define RESET_LOGIC_ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x495C))
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#define RESET_LOGIC_ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4960))
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#define RESET_LOGIC_ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4964))
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#define RESET_LOGIC_ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4968))
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#define RESET_LOGIC_ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4970))
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#define RESET_LOGIC_ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4974))
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#define RESET_LOGIC_ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4978))
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#define RESET_LOGIC_ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x497C))
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#define RESET_LOGIC_MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4980))
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#define RESET_LOGIC_MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x4984))
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#define RESET_LOGIC_MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x4988))
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#define RESET_LOGIC_MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4990))
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#define RESET_LOGIC_MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4994))
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#define RESET_LOGIC_MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4998))
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#define RESET_LOGIC_MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x499C))
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#define RESET_LOGIC_DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x49A0))
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#define RESET_LOGIC_DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x49A4))
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#define RESET_LOGIC_DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x49A8))
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#define RESET_LOGIC_DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x49B0))
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#define RESET_LOGIC_DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x49B4))
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#define RESET_LOGIC_DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x49B8))
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#define RESET_LOGIC_DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x49BC))
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#define RESET_LOGIC_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x49C0))
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#define RESET_LOGIC_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x49C4))
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#define RESET_LOGIC_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x49C8))
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#define RESET_LOGIC_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x49D0))
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#define RESET_LOGIC_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x49D4))
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#define RESET_LOGIC_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x49D8))
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#define RESET_LOGIC_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x49DC))
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#define MEMORY_CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4A20))
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#define MEMORY_CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4A24))
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#define MEMORY_CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4A28))
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#define MEMORY_CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4A30))
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#define MEMORY_CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4A34))
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#define MEMORY_CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4A38))
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#define MEMORY_CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4A3C))
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#define MEMORY_MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4A40))
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#define MEMORY_MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x4A44))
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#define MEMORY_MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x4A48))
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#define MEMORY_MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4A50))
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#define MEMORY_MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4A54))
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#define MEMORY_MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4A58))
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#define MEMORY_MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4A5C))
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#define MEMORY_G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4A60))
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#define MEMORY_G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x4A64))
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#define MEMORY_G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x4A68))
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#define MEMORY_G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4A70))
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#define MEMORY_G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4A74))
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#define MEMORY_G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4A78))
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#define MEMORY_G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4A7C))
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#define MEMORY_DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4A80))
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#define MEMORY_DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4A84))
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#define MEMORY_DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4A88))
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#define MEMORY_DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4A90))
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#define MEMORY_DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4A94))
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#define MEMORY_DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4A98))
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#define MEMORY_DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4A9C))
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#define MEMORY_CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4AA0))
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#define MEMORY_CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4AA4))
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#define MEMORY_CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4AA8))
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#define MEMORY_CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4AB0))
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#define MEMORY_CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4AB4))
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#define MEMORY_CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4AB8))
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#define MEMORY_CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4ABC))
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#define MEMORY_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4AC0))
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#define MEMORY_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x4AC4))
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#define MEMORY_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x4AC8))
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#define MEMORY_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4AD0))
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#define MEMORY_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4AD4))
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#define MEMORY_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4AD8))
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#define MEMORY_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4ADC))
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#define MEMORY_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4AE0))
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#define MEMORY_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4AE4))
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#define MEMORY_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4AE8))
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#define MEMORY_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4AF0))
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#define MEMORY_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4AF4))
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#define MEMORY_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4AF8))
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#define MEMORY_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4AFC))
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#define MEMORY_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4B00))
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#define MEMORY_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4B04))
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#define MEMORY_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4B08))
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#define MEMORY_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4B10))
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#define MEMORY_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4B14))
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#define MEMORY_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4B18))
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#define MEMORY_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4B1C))
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#define MEMORY_ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4B40))
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#define MEMORY_ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4B44))
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#define MEMORY_ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4B48))
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#define MEMORY_ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4B50))
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#define MEMORY_ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4B54))
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#define MEMORY_ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4B58))
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#define MEMORY_ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4B5C))
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#define MEMORY_ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4B60))
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#define MEMORY_ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4B64))
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#define MEMORY_ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4B68))
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#define MEMORY_ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4B70))
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#define MEMORY_ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4B74))
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#define MEMORY_ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4B78))
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#define MEMORY_ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4B7C))
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#define MEMORY_MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4B80))
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#define MEMORY_MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x4B84))
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#define MEMORY_MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x4B88))
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#define MEMORY_MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4B90))
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#define MEMORY_MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4B94))
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#define MEMORY_MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4B98))
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#define MEMORY_MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4B9C))
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#define MEMORY_DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4BA0))
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#define MEMORY_DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4BA4))
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#define MEMORY_DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4BA8))
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#define MEMORY_DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4BB0))
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#define MEMORY_DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4BB4))
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#define MEMORY_DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4BB8))
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#define MEMORY_DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4BBC))
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#define MEMORY_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4BC0))
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#define MEMORY_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4BC4))
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#define MEMORY_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4BC8))
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#define MEMORY_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4BD0))
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#define MEMORY_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4BD4))
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#define MEMORY_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4BD8))
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#define MEMORY_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4BDC))
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#define RESET_CMU_CAM0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4C20))
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#define RESET_CMU_CAM0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4C24))
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#define RESET_CMU_CAM0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4C28))
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#define RESET_CMU_CAM0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4C30))
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#define RESET_CMU_CAM0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4C34))
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#define RESET_CMU_CAM0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4C38))
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#define RESET_CMU_CAM0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4C3C))
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#define RESET_CMU_MSCL_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4C40))
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#define RESET_CMU_MSCL_STATUS ((void *)(PMU_ALIVE_BASE + 0x4C44))
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#define RESET_CMU_MSCL_OPTION ((void *)(PMU_ALIVE_BASE + 0x4C48))
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#define RESET_CMU_MSCL_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4C50))
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#define RESET_CMU_MSCL_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4C54))
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#define RESET_CMU_MSCL_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4C58))
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#define RESET_CMU_MSCL_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4C5C))
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#define RESET_CMU_G3D_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4C60))
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#define RESET_CMU_G3D_STATUS ((void *)(PMU_ALIVE_BASE + 0x4C64))
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#define RESET_CMU_G3D_OPTION ((void *)(PMU_ALIVE_BASE + 0x4C68))
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#define RESET_CMU_G3D_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4C70))
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#define RESET_CMU_G3D_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4C74))
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#define RESET_CMU_G3D_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4C78))
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#define RESET_CMU_G3D_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4C7C))
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#define RESET_CMU_DISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4C80))
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#define RESET_CMU_DISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4C84))
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#define RESET_CMU_DISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4C88))
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#define RESET_CMU_DISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4C90))
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#define RESET_CMU_DISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4C94))
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#define RESET_CMU_DISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4C98))
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#define RESET_CMU_DISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4C9C))
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#define RESET_CMU_CAM1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4CA0))
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#define RESET_CMU_CAM1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4CA4))
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#define RESET_CMU_CAM1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4CA8))
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#define RESET_CMU_CAM1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4CB0))
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#define RESET_CMU_CAM1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4CB4))
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#define RESET_CMU_CAM1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4CB8))
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#define RESET_CMU_CAM1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4CBC))
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#define RESET_CMU_AUD_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4CC0))
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#define RESET_CMU_AUD_STATUS ((void *)(PMU_ALIVE_BASE + 0x4CC4))
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#define RESET_CMU_AUD_OPTION ((void *)(PMU_ALIVE_BASE + 0x4CC8))
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#define RESET_CMU_AUD_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4CD0))
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#define RESET_CMU_AUD_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4CD4))
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#define RESET_CMU_AUD_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4CD8))
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#define RESET_CMU_AUD_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4CDC))
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#define RESET_CMU_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4CE0))
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#define RESET_CMU_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4CE4))
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#define RESET_CMU_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4CE8))
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#define RESET_CMU_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4CF0))
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#define RESET_CMU_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4CF4))
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#define RESET_CMU_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4CF8))
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#define RESET_CMU_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4CFC))
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#define RESET_CMU_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4D00))
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#define RESET_CMU_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4D04))
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#define RESET_CMU_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4D08))
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#define RESET_CMU_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4D10))
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#define RESET_CMU_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4D14))
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#define RESET_CMU_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4D18))
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#define RESET_CMU_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4D1C))
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#define RESET_CMU_ISP0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4D40))
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#define RESET_CMU_ISP0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4D44))
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#define RESET_CMU_ISP0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4D48))
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#define RESET_CMU_ISP0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4D50))
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#define RESET_CMU_ISP0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4D54))
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#define RESET_CMU_ISP0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4D58))
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#define RESET_CMU_ISP0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4D5C))
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#define RESET_CMU_ISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4D60))
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#define RESET_CMU_ISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4D64))
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#define RESET_CMU_ISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4D68))
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#define RESET_CMU_ISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4D70))
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#define RESET_CMU_ISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4D74))
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#define RESET_CMU_ISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4D78))
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#define RESET_CMU_ISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4D7C))
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#define RESET_CMU_MFC_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4D80))
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#define RESET_CMU_MFC_STATUS ((void *)(PMU_ALIVE_BASE + 0x4D84))
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#define RESET_CMU_MFC_OPTION ((void *)(PMU_ALIVE_BASE + 0x4D88))
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#define RESET_CMU_MFC_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4D90))
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#define RESET_CMU_MFC_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4D94))
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#define RESET_CMU_MFC_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4D98))
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#define RESET_CMU_MFC_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4D9C))
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#define RESET_CMU_DISP1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4DA0))
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#define RESET_CMU_DISP1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4DA4))
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#define RESET_CMU_DISP1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4DA8))
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#define RESET_CMU_DISP1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4DB0))
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#define RESET_CMU_DISP1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4DB4))
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#define RESET_CMU_DISP1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4DB8))
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#define RESET_CMU_DISP1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4DBC))
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#define RESET_CMU_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4DC0))
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#define RESET_CMU_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4DC4))
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#define RESET_CMU_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4DC8))
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#define RESET_CMU_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4DD0))
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#define RESET_CMU_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4DD4))
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#define RESET_CMU_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4DD8))
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#define RESET_CMU_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4DDC))
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#define RESET_SLEEP_FSYS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4EE0))
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#define RESET_SLEEP_FSYS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4EE4))
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#define RESET_SLEEP_FSYS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4EE8))
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#define RESET_SLEEP_FSYS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4EF0))
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#define RESET_SLEEP_FSYS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4EF4))
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#define RESET_SLEEP_FSYS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4EF8))
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#define RESET_SLEEP_FSYS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4EFC))
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#define RESET_SLEEP_BUS0_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4F00))
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#define RESET_SLEEP_BUS0_STATUS ((void *)(PMU_ALIVE_BASE + 0x4F04))
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#define RESET_SLEEP_BUS0_OPTION ((void *)(PMU_ALIVE_BASE + 0x4F08))
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#define RESET_SLEEP_BUS0_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4F10))
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#define RESET_SLEEP_BUS0_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4F14))
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#define RESET_SLEEP_BUS0_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4F18))
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#define RESET_SLEEP_BUS0_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4F1C))
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#define RESET_SLEEP_FSYS1_CONFIGURATION ((void *)(PMU_ALIVE_BASE + 0x4FC0))
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#define RESET_SLEEP_FSYS1_STATUS ((void *)(PMU_ALIVE_BASE + 0x4FC4))
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#define RESET_SLEEP_FSYS1_OPTION ((void *)(PMU_ALIVE_BASE + 0x4FC8))
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#define RESET_SLEEP_FSYS1_DURATION0 ((void *)(PMU_ALIVE_BASE + 0x4FD0))
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#define RESET_SLEEP_FSYS1_DURATION1 ((void *)(PMU_ALIVE_BASE + 0x4FD4))
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#define RESET_SLEEP_FSYS1_DURATION2 ((void *)(PMU_ALIVE_BASE + 0x4FD8))
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#define RESET_SLEEP_FSYS1_DURATION3 ((void *)(PMU_ALIVE_BASE + 0x4FDC))
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#define CLK_MUX_SEL_AUD ((void *)(PMU_ALIVE_BASE + 0x5000))
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#define CLK_MUX_STAT_AUD ((void *)(PMU_ALIVE_BASE + 0x5004))
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#define SYSTEM_INFO ((void *)(PMU_ALIVE_BASE + 0x5008))
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#define JTAG_DBG_DET ((void *)(PMU_ALIVE_BASE + 0x6000))
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#define MNGS_CORERST_LOCK ((void *)(PMU_ALIVE_BASE + 0x6004))
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#define APOLLO_CORERST_LOCK ((void *)(PMU_ALIVE_BASE + 0x6008))
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#define GPU_DVS_CTRL ((void *)(PMU_ALIVE_BASE + 0x6100))
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#define GPU_DVS_STATUS ((void *)(PMU_ALIVE_BASE + 0x6104))
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#define GPU_DVS_COUNTER ((void *)(PMU_ALIVE_BASE + 0x6108))
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#define GPU_DVS_CLK_CTRL ((void *)(PMU_ALIVE_BASE + 0x610C))
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#define IRQ_SELECTION ((void *)(PMU_ALIVE_BASE + 0x6800))
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#define DEK0 ((void *)(PMU_ALIVE_BASE + 0x7000))
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#define DEK1 ((void *)(PMU_ALIVE_BASE + 0x7004))
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#define DEK2 ((void *)(PMU_ALIVE_BASE + 0x7008))
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#define DEK3 ((void *)(PMU_ALIVE_BASE + 0x700C))
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#define DEK4 ((void *)(PMU_ALIVE_BASE + 0x7010))
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#define DEK5 ((void *)(PMU_ALIVE_BASE + 0x7014))
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#define DEK6 ((void *)(PMU_ALIVE_BASE + 0x7018))
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#define DEK7 ((void *)(PMU_ALIVE_BASE + 0x701C))
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#define DEK8 ((void *)(PMU_ALIVE_BASE + 0x7020))
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#define DEK9 ((void *)(PMU_ALIVE_BASE + 0x7024))
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#define DEK10 ((void *)(PMU_ALIVE_BASE + 0x7028))
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#define DEK11 ((void *)(PMU_ALIVE_BASE + 0x702C))
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#define DEK12 ((void *)(PMU_ALIVE_BASE + 0x7030))
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#define DEK13 ((void *)(PMU_ALIVE_BASE + 0x7034))
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#define DEK14 ((void *)(PMU_ALIVE_BASE + 0x7038))
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#define DEK15 ((void *)(PMU_ALIVE_BASE + 0x703C))
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#define LPI_MASK_APOLLO_ASB ((void *)(PMU_APOLLO_BASE + 0x0020))
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#define LPI_DENIAL_MASK_APOLLO_ASB ((void *)(PMU_APOLLO_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_APOLLO_ASB ((void *)(PMU_APOLLO_BASE + 0x0220))
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#define LPI_STATUS_APOLLO_ASB ((void *)(PMU_APOLLO_BASE + 0x0320))
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#define LPI_MASK_AUD_ASB ((void *)(PMU_AUD_BASE + 0x0020))
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#define LPI_DENIAL_MASK_AUD_ASB ((void *)(PMU_AUD_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_AUD_ASB ((void *)(PMU_AUD_BASE + 0x0220))
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#define LPI_STATUS_AUD_ASB ((void *)(PMU_AUD_BASE + 0x0320))
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#define LPI_MASK_BUS0_ASB ((void *)(PMU_BUS0_BASE + 0x0020))
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#define LPI_DENIAL_MASK_BUS0_ASB ((void *)(PMU_BUS0_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_BUS0_ASB ((void *)(PMU_BUS0_BASE + 0x0220))
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#define LPI_STATUS_BUS0_ASB ((void *)(PMU_BUS0_BASE + 0x0320))
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#define LPI_MASK_BUS1_ASB ((void *)(PMU_BUS1_BASE + 0x0020))
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#define LPI_DENIAL_MASK_BUS1_ASB ((void *)(PMU_BUS1_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_BUS1_ASB ((void *)(PMU_BUS1_BASE + 0x0220))
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#define LPI_STATUS_BUS1_ASB ((void *)(PMU_BUS1_BASE + 0x0320))
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#define LPI_MASK_CAM0_BUSMASTER ((void *)(PMU_CAM0_BASE + 0x0000))
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#define LPI_MASK_CAM0_ASB ((void *)(PMU_CAM0_BASE + 0x0020))
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#define LPI_DENIAL_MASK_CAM0_BUSMASTER ((void *)(PMU_CAM0_BASE + 0x0100))
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#define LPI_DENIAL_MASK_CAM0_ASB ((void *)(PMU_CAM0_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_CAM0_BUSMASTER ((void *)(PMU_CAM0_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_CAM0_ASB ((void *)(PMU_CAM0_BASE + 0x0220))
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#define LPI_STATUS_CAM0_BUSMASTER ((void *)(PMU_CAM0_BASE + 0x0300))
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#define LPI_STATUS_CAM0_ASB ((void *)(PMU_CAM0_BASE + 0x0320))
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#define LPI_MASK_CAM1_BUSMASTER ((void *)(PMU_CAM1_BASE + 0x0000))
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#define LPI_MASK_CAM1_ASB ((void *)(PMU_CAM1_BASE + 0x0020))
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#define LPI_DENIAL_MASK_CAM1_BUSMASTER ((void *)(PMU_CAM1_BASE + 0x0100))
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#define LPI_DENIAL_MASK_CAM1_ASB ((void *)(PMU_CAM1_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_CAM1_BUSMASTER ((void *)(PMU_CAM1_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_CAM1_ASB ((void *)(PMU_CAM1_BASE + 0x0220))
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#define LPI_STATUS_CAM1_BUSMASTER ((void *)(PMU_CAM1_BASE + 0x0300))
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#define LPI_STATUS_CAM1_ASB ((void *)(PMU_CAM1_BASE + 0x0320))
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#define LPI_MASK_CCORE_ASB ((void *)(PMU_CCORE_BASE + 0x0020))
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#define LPI_MASK_CCORE_DRAM ((void *)(PMU_CCORE_BASE + 0x0060))
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#define LPI_DENIAL_MASK_CCORE_ASB ((void *)(PMU_CCORE_BASE + 0x0120))
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#define LPI_DENIAL_MASK_CCORE_DRAM ((void *)(PMU_CCORE_BASE + 0x0160))
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#define LPI_AUTOMATIC_CLKGATE_CCORE_ASB ((void *)(PMU_CCORE_BASE + 0x0220))
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#define LPI_AUTOMATIC_CLKGATE_CCORE_DRAM ((void *)(PMU_CCORE_BASE + 0x0260))
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#define LPI_STATUS_CCORE_ASB ((void *)(PMU_CCORE_BASE + 0x0320))
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#define LPI_STATUS_CCORE_DRAM ((void *)(PMU_CCORE_BASE + 0x0360))
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#define LPI_MASK_DISP0_BUSMASTER ((void *)(PMU_DISP0_BASE + 0x0000))
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#define LPI_MASK_DISP0_ASB ((void *)(PMU_DISP0_BASE + 0x0020))
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#define LPI_DENIAL_MASK_DISP0_BUSMASTER ((void *)(PMU_DISP0_BASE + 0x0100))
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#define LPI_DENIAL_MASK_DISP0_ASB ((void *)(PMU_DISP0_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_DISP0_BUSMASTER ((void *)(PMU_DISP0_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_DISP0_ASB ((void *)(PMU_DISP0_BASE + 0x0220))
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#define LPI_STATUS_DISP0_BUSMASTER ((void *)(PMU_DISP0_BASE + 0x0300))
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#define LPI_STATUS_DISP0_ASB ((void *)(PMU_DISP0_BASE + 0x0320))
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#define LPI_MASK_DISP1_BUSMASTER ((void *)(PMU_DISP1_BASE + 0x0000))
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#define LPI_MASK_DISP1_ASB ((void *)(PMU_DISP1_BASE + 0x0020))
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#define LPI_DENIAL_MASK_DISP1_BUSMASTER ((void *)(PMU_DISP1_BASE + 0x0100))
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#define LPI_DENIAL_MASK_DISP1_ASB ((void *)(PMU_DISP1_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_DISP1_BUSMASTER ((void *)(PMU_DISP1_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_DISP1_ASB ((void *)(PMU_DISP1_BASE + 0x0220))
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#define LPI_STATUS_DISP1_BUSMASTER ((void *)(PMU_DISP1_BASE + 0x0300))
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#define LPI_STATUS_DISP1_ASB ((void *)(PMU_DISP1_BASE + 0x0320))
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#define LPI_MASK_FSYS0_BUSMASTER ((void *)(PMU_FSYS0_BASE + 0x0000))
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#define LPI_MASK_FSYS0_ASB ((void *)(PMU_FSYS0_BASE + 0x0020))
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#define LPI_DENIAL_MASK_FSYS0_BUSMASTER ((void *)(PMU_FSYS0_BASE + 0x0100))
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#define LPI_DENIAL_MASK_FSYS0_ASB ((void *)(PMU_FSYS0_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_FSYS0_BUSMASTER ((void *)(PMU_FSYS0_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_FSYS0_ASB ((void *)(PMU_FSYS0_BASE + 0x0220))
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#define LPI_STATUS_FSYS0_BUSMASTER ((void *)(PMU_FSYS0_BASE + 0x0300))
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#define LPI_STATUS_FSYS0_ASB ((void *)(PMU_FSYS0_BASE + 0x0320))
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#define LPI_MASK_FSYS1_BUSMASTER ((void *)(PMU_FSYS1_BASE + 0x0000))
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#define LPI_MASK_FSYS1_ASB ((void *)(PMU_FSYS1_BASE + 0x0020))
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#define LPI_DENIAL_MASK_FSYS1_BUSMASTER ((void *)(PMU_FSYS1_BASE + 0x0100))
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#define LPI_DENIAL_MASK_FSYS1_ASB ((void *)(PMU_FSYS1_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_FSYS1_BUSMASTER ((void *)(PMU_FSYS1_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_FSYS1_ASB ((void *)(PMU_FSYS1_BASE + 0x0220))
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#define LPI_STATUS_FSYS1_BUSMASTER ((void *)(PMU_FSYS1_BASE + 0x0300))
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#define LPI_STATUS_FSYS1_ASB ((void *)(PMU_FSYS1_BASE + 0x0320))
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#define LPI_MASK_G3D_ASB ((void *)(PMU_G3D_BASE + 0x0020))
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#define LPI_DENIAL_MASK_G3D_ASB ((void *)(PMU_G3D_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_G3D_ASB ((void *)(PMU_G3D_BASE + 0x0220))
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#define LPI_STATUS_G3D_ASB ((void *)(PMU_G3D_BASE + 0x0320))
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#define LPI_MASK_IMEM_BUSMASTER ((void *)(PMU_IMEM_BASE + 0x0000))
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#define LPI_MASK_IMEM_ASB ((void *)(PMU_IMEM_BASE + 0x0020))
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#define LPI_DENIAL_MASK_IMEM_BUSMASTER ((void *)(PMU_IMEM_BASE + 0x0100))
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#define LPI_DENIAL_MASK_IMEM_ASB ((void *)(PMU_IMEM_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_IMEM_BUSMASTER ((void *)(PMU_IMEM_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_IMEM_ASB ((void *)(PMU_IMEM_BASE + 0x0220))
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#define LPI_STATUS_IMEM_BUSMASTER ((void *)(PMU_IMEM_BASE + 0x0300))
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#define LPI_STATUS_IMEM_ASB ((void *)(PMU_IMEM_BASE + 0x0320))
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#define LPI_MASK_ISP0_BUSMASTER ((void *)(PMU_ISP0_BASE + 0x0000))
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#define LPI_MASK_ISP0_ASB ((void *)(PMU_ISP0_BASE + 0x0020))
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#define LPI_DENIAL_MASK_ISP0_BUSMASTER ((void *)(PMU_ISP0_BASE + 0x0100))
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#define LPI_DENIAL_MASK_ISP0_ASB ((void *)(PMU_ISP0_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_ISP0_BUSMASTER ((void *)(PMU_ISP0_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_ISP0_ASB ((void *)(PMU_ISP0_BASE + 0x0220))
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#define LPI_STATUS_ISP0_BUSMASTER ((void *)(PMU_ISP0_BASE + 0x0300))
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#define LPI_STATUS_ISP0_ASB ((void *)(PMU_ISP0_BASE + 0x0320))
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#define LPI_MASK_ISP1_BUSMASTER ((void *)(PMU_ISP1_BASE + 0x0000))
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#define LPI_MASK_ISP1_ASB ((void *)(PMU_ISP1_BASE + 0x0020))
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#define LPI_DENIAL_MASK_ISP1_BUSMASTER ((void *)(PMU_ISP1_BASE + 0x0100))
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#define LPI_DENIAL_MASK_ISP1_ASB ((void *)(PMU_ISP1_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_ISP1_BUSMASTER ((void *)(PMU_ISP1_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_ISP1_ASB ((void *)(PMU_ISP1_BASE + 0x0220))
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#define LPI_STATUS_ISP1_BUSMASTER ((void *)(PMU_ISP1_BASE + 0x0300))
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#define LPI_STATUS_ISP1_ASB ((void *)(PMU_ISP1_BASE + 0x0320))
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#define LPI_MASK_MFC_BUSMASTER ((void *)(PMU_MFC_BASE + 0x0000))
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#define LPI_MASK_MFC_ASB ((void *)(PMU_MFC_BASE + 0x0020))
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#define LPI_DENIAL_MASK_MFC_BUSMASTER ((void *)(PMU_MFC_BASE + 0x0100))
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#define LPI_DENIAL_MASK_MFC_ASB ((void *)(PMU_MFC_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_MFC_BUSMASTER ((void *)(PMU_MFC_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_MFC_ASB ((void *)(PMU_MFC_BASE + 0x0220))
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#define LPI_STATUS_MFC_BUSMASTER ((void *)(PMU_MFC_BASE + 0x0300))
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#define LPI_STATUS_MFC_ASB ((void *)(PMU_MFC_BASE + 0x0320))
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#define LPI_MASK_MIF_ASB_MIF0 ((void *)(PMU_MIF0_BASE + 0x0020))
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#define LPI_MASK_MIF_DRAM_MIF0 ((void *)(PMU_MIF0_BASE + 0x0060))
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#define LPI_DENIAL_MASK_MIF_ASB_MIF0 ((void *)(PMU_MIF0_BASE + 0x0120))
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#define LPI_DENIAL_MASK_MIF_DRAM_MIF0 ((void *)(PMU_MIF0_BASE + 0x0160))
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#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF0 ((void *)(PMU_MIF0_BASE + 0x0220))
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#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF0 ((void *)(PMU_MIF0_BASE + 0x0260))
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#define LPI_STATUS_MIF_ASB_MIF0 ((void *)(PMU_MIF0_BASE + 0x0320))
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#define LPI_MASK_MIF_ASB_MIF1 ((void *)(PMU_MIF1_BASE + 0x0020))
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#define LPI_MASK_MIF_DRAM_MIF1 ((void *)(PMU_MIF1_BASE + 0x0060))
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#define LPI_DENIAL_MASK_MIF_ASB_MIF1 ((void *)(PMU_MIF1_BASE + 0x0120))
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#define LPI_DENIAL_MASK_MIF_DRAM_MIF1 ((void *)(PMU_MIF1_BASE + 0x0160))
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#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF1 ((void *)(PMU_MIF1_BASE + 0x0220))
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#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF1 ((void *)(PMU_MIF1_BASE + 0x0260))
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#define LPI_STATUS_MIF_ASB_MIF1 ((void *)(PMU_MIF1_BASE + 0x0320))
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#define LPI_MASK_MIF_ASB_MIF2 ((void *)(PMU_MIF2_BASE + 0x0020))
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#define LPI_MASK_MIF_DRAM_MIF2 ((void *)(PMU_MIF2_BASE + 0x0060))
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#define LPI_DENIAL_MASK_MIF_ASB_MIF2 ((void *)(PMU_MIF2_BASE + 0x0120))
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#define LPI_DENIAL_MASK_MIF_DRAM_MIF2 ((void *)(PMU_MIF2_BASE + 0x0160))
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#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF2 ((void *)(PMU_MIF2_BASE + 0x0220))
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#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF2 ((void *)(PMU_MIF2_BASE + 0x0260))
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#define LPI_STATUS_MIF_ASB_MIF2 ((void *)(PMU_MIF2_BASE + 0x0320))
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#define LPI_MASK_MIF_ASB_MIF3 ((void *)(PMU_MIF3_BASE + 0x0020))
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#define LPI_MASK_MIF_DRAM_MIF3 ((void *)(PMU_MIF3_BASE + 0x0060))
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#define LPI_DENIAL_MASK_MIF_ASB_MIF3 ((void *)(PMU_MIF3_BASE + 0x0120))
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#define LPI_DENIAL_MASK_MIF_DRAM_MIF3 ((void *)(PMU_MIF3_BASE + 0x0160))
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#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF3 ((void *)(PMU_MIF3_BASE + 0x0220))
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#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF3 ((void *)(PMU_MIF3_BASE + 0x0260))
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#define LPI_STATUS_MIF_ASB_MIF3 ((void *)(PMU_MIF3_BASE + 0x0320))
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#define LPI_MASK_MNGS_BUSMASTER ((void *)(PMU_MNGS_BASE + 0x0000))
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#define LPI_MASK_MNGS_ASB ((void *)(PMU_MNGS_BASE + 0x0020))
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#define LPI_DENIAL_MASK_MNGS_BUSMASTER ((void *)(PMU_MNGS_BASE + 0x0100))
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#define LPI_DENIAL_MASK_MNGS_ASB ((void *)(PMU_MNGS_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_MNGS_BUSMASTER ((void *)(PMU_MNGS_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_MNGS_ASB ((void *)(PMU_MNGS_BASE + 0x0220))
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#define LPI_STATUS_MNGS_BUSMASTER ((void *)(PMU_MNGS_BASE + 0x0300))
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#define LPI_STATUS_MNGS_ASB ((void *)(PMU_MNGS_BASE + 0x0320))
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#define LPI_MASK_MSCL_BUSMASTER ((void *)(PMU_MSCL_BASE + 0x0000))
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#define LPI_MASK_MSCL_ASB ((void *)(PMU_MSCL_BASE + 0x0020))
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#define LPI_DENIAL_MASK_MSCL_BUSMASTER ((void *)(PMU_MSCL_BASE + 0x0100))
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#define LPI_DENIAL_MASK_MSCL_ASB ((void *)(PMU_MSCL_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_MSCL_BUSMASTER ((void *)(PMU_MSCL_BASE + 0x0200))
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#define LPI_AUTOMATIC_CLKGATE_MSCL_ASB ((void *)(PMU_MSCL_BASE + 0x0220))
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#define LPI_STATUS_MSCL_BUSMASTER ((void *)(PMU_MSCL_BASE + 0x0300))
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#define LPI_STATUS_MSCL_ASB ((void *)(PMU_MSCL_BASE + 0x0320))
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#define LPI_MASK_PERIC0_ASB ((void *)(PMU_PERIC0_BASE + 0x0020))
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#define LPI_DENIAL_MASK_PERIC0_ASB ((void *)(PMU_PERIC0_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_PERIC0_ASB ((void *)(PMU_PERIC0_BASE + 0x0220))
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#define LPI_STATUS_PERIC0_ASB ((void *)(PMU_PERIC0_BASE + 0x0320))
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#define LPI_MASK_PERIC1_ASB ((void *)(PMU_PERIC1_BASE + 0x0020))
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#define LPI_DENIAL_MASK_PERIC1_ASB ((void *)(PMU_PERIC1_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_PERIC1_ASB ((void *)(PMU_PERIC1_BASE + 0x0220))
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#define LPI_STATUS_PERIC1_ASB ((void *)(PMU_PERIC1_BASE + 0x0320))
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#define LPI_MASK_PERIS_ASB ((void *)(PMU_PERIS_BASE + 0x0020))
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#define LPI_DENIAL_MASK_PERIS_ASB ((void *)(PMU_PERIS_BASE + 0x0120))
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#define LPI_AUTOMATIC_CLKGATE_PERIS_ASB ((void *)(PMU_PERIS_BASE + 0x0220))
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#define LPI_STATUS_PERIS_ASB ((void *)(PMU_PERIS_BASE + 0x0320))
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#endif
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