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svp minor adjustments
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@326 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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67256d4b2c
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1 changed files with 31 additions and 37 deletions
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@ -136,7 +136,6 @@
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* mld (rj), (ri) [, b]
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* operation: A = 0; P = (rj) * (ri)
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* notes: based on IIR_4B.SC sample. flags? what is b???
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* TODO: figure out if (rj) and (ri) get loaded in X and Y
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*
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* mpya (rj), (ri) [, b]
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* name: multiply and add?
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@ -238,11 +237,6 @@
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if (!rA32) rST |= SSP_FLAG_Z; \
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else rST |= (rA32>>16)&SSP_FLAG_N;
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#define UPD_t_LZVN \
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rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
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if (!t) rST |= SSP_FLAG_Z; \
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else rST |= t&SSP_FLAG_N; \
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// standard cond processing.
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// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
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#define COND_CHECK \
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@ -250,7 +244,7 @@
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case 0x00: cond = 1; break; /* always true */ \
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case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
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case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
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default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
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default:elprintf(EL_SVP, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
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}
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// ops with accumulator.
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@ -260,64 +254,64 @@
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ssp->gr[SSP_A].h = x
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#define OP_LDA32(x) \
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ssp->gr[SSP_A].v = x
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rA32 = x
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#define OP_SUBA(x) { \
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u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
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UPD_t_LZVN \
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ssp->gr[SSP_A].h = t; \
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rA32 -= (x) << 16; \
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UPD_LZVN \
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}
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#define OP_SUBA32(x) { \
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ssp->gr[SSP_A].v -= (x); \
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rA32 -= (x); \
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UPD_LZVN \
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}
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#define OP_CMPA(x) { \
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u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
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UPD_t_LZVN \
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u32 t = rA32 - ((x) << 16); \
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rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
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if (!t) rST |= SSP_FLAG_Z; \
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else rST |= (t>>16)&SSP_FLAG_N; \
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}
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#define OP_CMPA32(x) { \
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u32 t = ssp->gr[SSP_A].v - (x); \
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u32 t = rA32 - (x); \
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rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
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if (!t) rST |= SSP_FLAG_Z; \
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else rST |= (t>>16)&SSP_FLAG_N; \
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}
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#define OP_ADDA(x) { \
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u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
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UPD_t_LZVN \
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ssp->gr[SSP_A].h = t; \
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rA32 += (x) << 16; \
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UPD_LZVN \
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}
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#define OP_ADDA32(x) { \
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ssp->gr[SSP_A].v += (x); \
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rA32 += (x); \
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UPD_LZVN \
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}
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#define OP_ANDA(x) \
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ssp->gr[SSP_A].v &= (x) << 16; \
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rA32 &= (x) << 16; \
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UPD_ACC_ZN
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#define OP_ANDA32(x) \
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ssp->gr[SSP_A].v &= (x); \
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rA32 &= (x); \
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UPD_ACC_ZN
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#define OP_ORA(x) \
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ssp->gr[SSP_A].v |= (x) << 16; \
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rA32 |= (x) << 16; \
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UPD_ACC_ZN
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#define OP_ORA32(x) \
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ssp->gr[SSP_A].v |= (x); \
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rA32 |= (x); \
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UPD_ACC_ZN
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#define OP_EORA(x) \
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ssp->gr[SSP_A].v ^= (x) << 16; \
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rA32 ^= (x) << 16; \
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UPD_ACC_ZN
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#define OP_EORA32(x) \
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ssp->gr[SSP_A].v ^= (x); \
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rA32 ^= (x); \
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UPD_ACC_ZN
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@ -1026,7 +1020,7 @@ void ssp1601_run(int cycles)
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if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
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// not sure. MAME claims that only hi word is transfered.
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read_P(); // update P
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ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
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rA32 = ssp->gr[SSP_P].v;
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}
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else
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{
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@ -1109,8 +1103,8 @@ void ssp1601_run(int cycles)
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// very uncertain about this one. What about b?
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if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
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read_P(); // update P
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ssp->gr[SSP_A].v -= ssp->gr[SSP_P].v; // maybe only upper word?
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// UPD_ACC_ZN // I've seen code checking flags after this
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rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
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// UPD_ACC_ZN // I've seen code checking flags after this
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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break;
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@ -1120,7 +1114,7 @@ void ssp1601_run(int cycles)
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// dunno if this is correct. What about b?
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if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
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read_P(); // update P
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ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
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rA32 += ssp->gr[SSP_P].v; // maybe only upper word?
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UPD_ACC_ZN // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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@ -1130,8 +1124,8 @@ void ssp1601_run(int cycles)
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case 0x5b:
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// dunno if this is correct. What about b?
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if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
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ssp->gr[SSP_A].v = 0; // maybe only upper word?
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// UPD_t_LZVN // ?
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rA32 = 0; // maybe only upper word?
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rST &= 0x0fff; // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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break;
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@ -1186,13 +1180,13 @@ void ssp1601_run(int cycles)
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case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
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// OP simm
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case 0x1c: OP_SUBA(op & 0xff); break;
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case 0x3c: OP_CMPA(op & 0xff); break;
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case 0x4c: OP_ADDA(op & 0xff); break;
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case 0x1c: OP_SUBA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
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case 0x3c: OP_CMPA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
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case 0x4c: OP_ADDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
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// MAME code only does LSB of top word, but this looks wrong to me.
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case 0x5c: OP_ANDA(op & 0xff); break;
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case 0x6c: OP_ORA (op & 0xff); break;
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case 0x7c: OP_EORA(op & 0xff); break;
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case 0x5c: OP_ANDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
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case 0x6c: OP_ORA (op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
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case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
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default:
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elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
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