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https://github.com/RaySollium99/picodrive.git
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overhaul of the register cache (improves generated code by some 10+%)
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kub
parent
e267031a50
commit
4f4e9bf3bd
4 changed files with 1455 additions and 667 deletions
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@ -5,6 +5,7 @@
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*/
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#define HOST_REGS 16
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#define CONTEXT_REG 11
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#define RET_REG 0
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@ -406,9 +407,24 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_add_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ADD_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_addf_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ADD_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_addf_r_r_r_lsr(d, s1, s2, lslimm) \
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EOP_ADD_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSR,lslimm)
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#define emith_adcf_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ADC_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_sub_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_SUB_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_subf_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_SUB_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_sbcf_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_SBC_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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@ -418,6 +434,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) \
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EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSR,lsrimm)
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#define emith_and_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_AND_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_or_r_r_lsl(d, s, lslimm) \
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emith_or_r_r_r_lsl(d, d, s, lslimm)
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@ -427,12 +446,30 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_add_r_r_r(d, s1, s2) \
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emith_add_r_r_r_lsl(d, s1, s2, 0)
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#define emith_addf_r_r_r(d, s1, s2) \
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emith_addf_r_r_r_lsl(d, s1, s2, 0)
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#define emith_adcf_r_r_r(d, s1, s2) \
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emith_adcf_r_r_r_lsl(d, s1, s2, 0)
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#define emith_sub_r_r_r(d, s1, s2) \
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emith_sub_r_r_r_lsl(d, s1, s2, 0)
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#define emith_subf_r_r_r(d, s1, s2) \
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emith_subf_r_r_r_lsl(d, s1, s2, 0)
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#define emith_sbcf_r_r_r(d, s1, s2) \
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emith_sbcf_r_r_r_lsl(d, s1, s2, 0)
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#define emith_or_r_r_r(d, s1, s2) \
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emith_or_r_r_r_lsl(d, s1, s2, 0)
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#define emith_eor_r_r_r(d, s1, s2) \
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emith_eor_r_r_r_lsl(d, s1, s2, 0)
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#define emith_and_r_r_r(d, s1, s2) \
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emith_and_r_r_r_lsl(d, s1, s2, 0)
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#define emith_add_r_r(d, s) \
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emith_add_r_r_r(d, d, s)
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@ -539,11 +576,14 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_BIC, r, imm)
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#define emith_tst_r_imm_c(cond, r, imm) \
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emith_top_imm(cond, A_OP_TST, r, imm)
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#define emith_move_r_imm_s8(r, imm) { \
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if ((imm) & 0x80) \
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EOP_MVN_IMM(r, 0, ((imm) ^ 0xff)); \
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if ((s8)(imm) < 0) \
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EOP_MVN_IMM(r, 0, ((u8)(imm) ^ 0xff)); \
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else \
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EOP_MOV_IMM(r, 0, imm); \
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EOP_MOV_IMM(r, 0, (u8)imm); \
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}
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#define emith_and_r_r_imm(d, s, imm) \
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@ -558,6 +598,15 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_sub_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm)
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#define emith_subf_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 1, A_OP_SUB, d, s, (imm))
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#define emith_or_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_ORR, d, s, (imm))
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#define emith_eor_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_EOR, d, s, (imm))
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#define emith_neg_r_r(d, s) \
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EOP_RSB_IMM(d, s, 0, 0)
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@ -15,6 +15,7 @@
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enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define HOST_REGS 8
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#define CONTEXT_REG xBP
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#define RET_REG xAX
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@ -185,6 +186,61 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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} \
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} while (0)
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#define emith_sub_r_r_r(d, s1, s2) do { \
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if (d == s1) { \
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emith_sub_r_r(d, s2); \
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} else if (d == s2) { \
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emith_sub_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_sub_r_r(d, s2); \
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} \
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} while (0)
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#define emith_adc_r_r_r(d, s1, s2) do { \
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if (d == s1) { \
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emith_adc_r_r(d, s2); \
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} else if (d == s2) { \
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emith_adc_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_adc_r_r(d, s2); \
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} \
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} while (0)
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#define emith_sbc_r_r_r(d, s1, s2) do { \
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if (d == s1) { \
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emith_sbc_r_r(d, s2); \
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} else if (d == s2) { \
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emith_sbc_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_sbc_r_r(d, s2); \
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} \
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} while (0)
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#define emith_and_r_r_r(d, s1, s2) do { \
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if (d == s1) { \
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emith_and_r_r(d, s2); \
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} else if (d == s2) { \
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emith_and_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_and_r_r(d, s2); \
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} \
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} while (0)
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#define emith_or_r_r_r(d, s1, s2) do { \
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if (d == s1) { \
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emith_or_r_r(d, s2); \
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} else if (d == s2) { \
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emith_or_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_or_r_r(d, s2); \
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} \
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} while (0)
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#define emith_eor_r_r_r(d, s1, s2) do { \
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if (d == s1) { \
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emith_eor_r_r(d, s2); \
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@ -281,6 +337,8 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_eor_r_imm(r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_bic_r_imm(r, imm)
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#define emith_tst_r_imm_c(cond, r, imm) \
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emith_tst_r_imm(r, imm)
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#define emith_ror_c(cond, d, s, cnt) \
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emith_ror(d, s, cnt)
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@ -324,12 +382,33 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT(imm, s32); \
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} while (0)
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#define emith_sub_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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if (imm) \
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emith_sub_r_imm(d, imm); \
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} while (0)
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#define emith_and_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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emith_and_r_imm(d, imm); \
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} while (0)
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#define emith_or_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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if ((s32)imm != 0) \
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emith_or_r_imm(d, imm); \
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} while (0)
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#define emith_eor_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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if ((s32)imm != 0) \
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emith_eor_r_imm(d, imm); \
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} while (0)
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// shift
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#define emith_shift(op, d, s, cnt) do { \
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if (d != s) \
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@ -456,6 +535,14 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_eorf_r_r emith_eor_r_r
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#define emith_negcf_r_r emith_negc_r_r
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#define emith_subf_r_r_imm emith_sub_r_r_imm
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#define emith_addf_r_r_r emith_add_r_r_r
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#define emith_subf_r_r_r emith_sub_r_r_r
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#define emith_adcf_r_r_r emith_adc_r_r_r
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#define emith_sbcf_r_r_r emith_sbc_r_r_r
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#define emith_eorf_r_r_r emith_eor_r_r_r
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#define emith_addf_r_r_r_lsr emith_add_r_r_r_lsr
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#define emith_lslf emith_lsl
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#define emith_lsrf emith_lsr
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#define emith_asrf emith_asr
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@ -705,7 +792,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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case 0: rd = xDI; break; \
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case 1: rd = xSI; break; \
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case 2: rd = xDX; break; \
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case 3: rd = xBX; break; \
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default: rd = xCX; break; \
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}
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#define emith_sh2_drc_entry() { \
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@ -728,6 +815,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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case 0: rd = xCX; break; \
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case 1: rd = xDX; break; \
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case 2: rd = 8; break; \
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default: rd = 9; break; \
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}
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#define emith_sh2_drc_entry() { \
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@ -764,6 +852,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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case 0: rd = xAX; break; \
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case 1: rd = xDX; break; \
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case 2: rd = xCX; break; \
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default: rd = xBX; break; \
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}
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#define emith_sh2_drc_entry() { \
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1972
cpu/sh2/compiler.c
1972
cpu/sh2/compiler.c
File diff suppressed because it is too large
Load diff
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@ -31,8 +31,10 @@ void scan_block(unsigned int base_pc, int is_slave,
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// XXX MUST match definitions in cpu/sh2/compiler.c
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#if defined(__arm__)
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#define DRC_SR_REG r10
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#elif defined(__i386__) || defined(__x86_64__)
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#elif defined(__i386__)
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#define DRC_SR_REG edi
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#elif defined(__x86_64__)
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#define DRC_SR_REG ebx
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#else
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#warning "direct DRC register access not available for this host"
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#endif
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