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sh2 drc: bug fixing

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This commit is contained in:
kub 2019-11-27 21:02:53 +01:00
parent f1da0a362f
commit 57d863cb87
4 changed files with 28 additions and 21 deletions
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2
cpu/drc/emit_arm64.c
View file

@ -25,7 +25,7 @@
#define PR 18 // platform register
// All operations but ptr ops are using the lower 32 bits of the A64 registers.
// The upper 32 bits are only used in ptr ops.
// The upper 32 bits are only used in ptr ops and are zeroed by A64 32 bit ops.
#define A64_COND_EQ 0x0

10
cpu/drc/emit_mips.c
View file

@ -33,6 +33,8 @@
#define FC 24 // emulated processor flags: C (bit 0), others 0
#define FV 25 // emulated processor flags: Nt^Ns (bit 31). others x
// All operations but ptr ops are using the lower 32 bits of the registers.
// The upper 32 bits always contain the sign extension from the lower 32 bits.
// unified conditions; virtual, not corresponding to anything real on MIPS
#define DCOND_EQ 0x0
@ -1095,10 +1097,10 @@ static void emith_lohi_nops(void)
emith_lohi_nops(); \
EMIT(MIPS_MULT(s1, s2)); \
EMIT(MIPS_MFLO(AT)); \
emith_add_r_r(dlo, AT); \
EMIT(MIPS_SLTU_REG(t_, dlo, AT)); \
EMIT(MIPS_MFHI(AT)); \
EMIT(MIPS_MFHI(t_)); \
last_lohi = (u8 *)tcache_ptr; \
emith_add_r_r(dlo, AT); \
EMIT(MIPS_SLTU_REG(AT, dlo, AT)); \
emith_add_r_r(dhi, AT); \
emith_add_r_r(dhi, t_); \
rcache_free_tmp(t_); \
@ -1479,7 +1481,7 @@ static int emith_cond_check(int cond, int *r)
// NB: ABI SP alignment is 8 for compatibility with MIPS IV
#define emith_push_ret(r) do { \
emith_add_r_r_ptr_imm(SP, SP, -8-16); /* ABI: 16 byte arg save area */ \
emith_add_r_r_ptr_imm(SP, SP, -8-16); /* O32: 16 byte arg save area */ \
emith_write_r_r_offs(LR, SP, 4+16); \
if ((r) > 0) emith_write_r_r_offs(r, SP, 0+16); \
} while (0)

9
cpu/drc/emit_riscv.c
View file

@ -30,6 +30,8 @@
#define FC 29 // emulated processor flags: C (bit 0), others 0
#define FV 28 // emulated processor flags: Nt^Ns (bit 31). others x
// All operations but ptr ops are using the lower 32 bits of the registers.
// The upper 32 bits always contain the sign extension from the lower 32 bits.
// unified conditions; virtual, not corresponding to anything real on RISC-V
#define DCOND_EQ 0x0
@ -217,12 +219,9 @@ enum { F2_ALT=0x20, F2_MULDIV=0x01 };
// NB: must split 64 bit result into 2 32 bit registers
// NB: expects 32 bit values in s1+s2, correctly sign extended to 64 bits
#define EMIT_R5_MULLU_REG(dlo, dhi, s1, s2) do { \
/*EMIT(R5_ADDW_IMM(s1, s1, 0));*/ \
/*EMIT(R5_ADDW_IMM(s2, s2, 0));*/ \
EMIT(R5_MUL(dlo, s1, s2)); \
EMIT(R5_ASR_IMM(dhi, dlo, 32)); \
EMIT(R5_LSL_IMM(dlo, dlo, 32)); \
EMIT(R5_ASR_IMM(dlo, dlo, 32)); \
EMIT(R5_ADDW_IMM(dlo, dlo, 0)); \
} while (0)
#define EMIT_R5_MULLS_REG(dlo, dhi, s1, s2) \
@ -633,7 +632,7 @@ static int literal_pindex, literal_iindex;
static inline int emith_pool_literal(uintptr_t imm)
{
int idx = literal_pindex - 8; // max look behind in pool
// see if one of the last literals was the same (or close enough)
// see if one of the last literals was the same
for (idx = (idx < 0 ? 0 : idx); idx < literal_pindex; idx++)
if (imm == literal_pool[idx])
break;