mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
sh2 memory interface optimzations
This commit is contained in:
kub
parent
4f4e9bf3bd
commit
6822ba9d64
10 changed files with 585 additions and 157 deletions
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@ -65,6 +65,9 @@
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#define DCOND_VS A_COND_VS
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#define DCOND_VC A_COND_VC
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#define DCOND_CS A_COND_HS
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#define DCOND_CC A_COND_LO
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/* addressing mode 1 */
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#define A_AM1_LSL 0
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#define A_AM1_LSR 1
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@ -184,8 +187,10 @@
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#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
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#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_LDRB_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,1,1,rn,rd,shift_imm,A_AM1_LSL,rm);
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#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_REG2(cond,rd,rn,rm) EOP_C_AM3_REG(cond,1,1,rn,rd,0,1,rm)
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#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
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@ -479,6 +484,8 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_adc_r_r(d, s) \
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EOP_ADC_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_and_r_r_c(cond, d, s) \
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EOP_AND_REG(cond,0,d,d,s,A_AM1_LSL,0)
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#define emith_and_r_r(d, s) \
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EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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@ -677,12 +684,24 @@ static int emith_xbranch(int cond, void *target, int is_call)
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// misc
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#define emith_read_r_r_offs_c(cond, r, rs, offs) \
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EOP_LDR_IMM2(cond, r, rs, offs)
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#define emith_read_r_r_r_c(cond, r, rs, rm) \
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EOP_LDR_REG_LSL(cond, r, rs, rm, 0)
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#define emith_read_r_r_r(r, rs, rm) \
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EOP_LDR_REG_LSL(A_COND_AL, r, rs, rm, 0)
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#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
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EOP_LDRB_IMM2(cond, r, rs, offs)
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#define emith_read8_r_r_r_c(cond, r, rs, rm) \
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EOP_LDRB_REG_LSL(cond, r, rs, rm, 0)
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#define emith_read8_r_r_r(r, rs, rm) \
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EOP_LDRB_REG_LSL(A_COND_AL, r, rs, rm, 0)
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#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
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EOP_LDRH_IMM2(cond, r, rs, offs)
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#define emith_read16_r_r_r_c(cond, r, rs, rm) \
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EOP_LDRH_REG2(cond, r, rs, rm)
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#define emith_read16_r_r_r(r, rs, rm) \
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EOP_LDRH_REG2(A_COND_AL, r, rs, rm)
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#define emith_read_r_r_offs(r, rs, offs) \
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emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
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@ -844,11 +863,20 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_sh2_drc_exit() \
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EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R15M)
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#define emith_sh2_wcall(a, tab) { \
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emith_lsr(12, a, SH2_WRITE_SHIFT); \
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EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
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emith_move_r_r(2, CONTEXT_REG); \
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emith_jump_reg(12); \
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// assumes a is in arg0, tab, func and mask are temp
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#define emith_sh2_rcall(a, tab, func, mask) { \
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emith_lsr(mask, a, SH2_READ_SHIFT); \
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EOP_ADD_REG_LSL(tab, tab, mask, 3); \
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EOP_LDMIA(tab, (1<<func)|(1<<mask)); \
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emith_addf_r_r_r(func,func,func); \
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}
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// assumes a, val are in arg0 and arg1, tab and func are temp
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#define emith_sh2_wcall(a, val, tab, func) { \
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emith_lsr(func, a, SH2_WRITE_SHIFT); \
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EOP_LDR_REG_LSL(A_COND_AL,func,tab,func,2); \
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emith_move_r_r(2, CONTEXT_REG); /* arg2 */ \
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emith_jump_reg(func); \
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}
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#define emith_sh2_dtbf_loop() { \
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@ -52,6 +52,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define DCOND_VS ICOND_JO // oVerflow Set
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#define DCOND_VC ICOND_JNO // oVerflow Clear
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#define DCOND_CS ICOND_JB // carry set
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#define DCOND_CC ICOND_JAE // carry clear
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#define EMIT_PTR(ptr, val, type) \
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*(type *)(ptr) = val
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@ -118,6 +121,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_add_r_r(d, s) \
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EMIT_OP_MODRM(0x01, 3, s, d)
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#define emith_add_r_r_ptr(d, s) do { \
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EMIT_REX_IF(1, dst, src); \
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EMIT_OP_MODRM64(0x01, 3, s, d); \
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} while (0)
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#define emith_sub_r_r(d, s) \
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EMIT_OP_MODRM(0x29, 3, s, d)
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@ -341,6 +349,15 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_tst_r_imm(r, imm)
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#define emith_ror_c(cond, d, s, cnt) \
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emith_ror(d, s, cnt)
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#define emith_and_r_r_c(cond, d, s) \
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emith_and_r_r(d, s);
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#define emith_read8_r_r_r_c(cond, r, rs, rm) \
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emith_read8_r_r_r(r, rs, rm)
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#define emith_read16_r_r_r_c(cond, r, rs, rm) \
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emith_read16_r_r_r(r, rs, rm)
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#define emith_read_r_r_r_c(cond, r, rs, rm) \
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emith_read_r_r_r(r, rs, rm)
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#define emith_read_r_r_offs_c(cond, r, rs, offs) \
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emith_read_r_r_offs(r, rs, offs)
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@ -621,6 +638,30 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_write_r_r_offs(r, rs, offs); \
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} while (0)
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#define emith_read8_r_r_r(r, rs, rm) do { \
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int r_ = r; \
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if (!is_abcdx(r)) \
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r_ = rcache_get_tmp(); \
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EMIT(0x0f, u8); \
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EMIT_OP_MODRM(0xb6, 0, r, 4); \
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EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
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if ((r) != r_) { \
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emith_move_r_r(r, r_); \
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rcache_free_tmp(r_); \
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} \
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} while (0)
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#define emith_read16_r_r_r(r, rs, rm) do { \
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EMIT(0x0f, u8); \
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EMIT_OP_MODRM(0xb7, 0, r, 4); \
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EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
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} while (0)
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#define emith_read_r_r_r(r, rs, rm) do { \
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EMIT_OP_MODRM(0x8b, 0, r, 4); \
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EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
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} while (0)
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#define emith_ctx_read(r, offs) \
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emith_read_r_r_offs(r, CONTEXT_REG, offs)
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@ -888,15 +929,30 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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if ((mask) & (1 << xAX)) emith_pop(xAX); \
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} while (0)
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#define emith_sh2_wcall(a, tab) { \
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#define emith_sh2_rcall(a, tab, func, mask) { \
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emith_lsr(mask, a, SH2_READ_SHIFT); \
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EMIT_REX_IF(1, mask, tab); \
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EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
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EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
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EMIT_REX_IF(1, mask, tab); \
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EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
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EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
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EMIT_REX_IF(1, func, tab); \
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EMIT_OP_MODRM64(0x8b, 0, func, tab); /* mov func, [tab] */ \
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EMIT_OP_MODRM64(0x8b, 1, mask, tab); \
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EMIT(1 << PTR_SCALE, u8); /* mov mask, [tab + {4,8}] */ \
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emith_add_r_r_ptr(func, func); \
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}
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#define emith_sh2_wcall(a, val, tab, func) { \
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int arg2_; \
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host_arg2reg(arg2_, 2); \
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emith_lsr(NA_TMP_REG, a, SH2_WRITE_SHIFT); \
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EMIT_REX_IF(1, NA_TMP_REG, tab); \
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EMIT_OP_MODRM64(0x8b, 0, NA_TMP_REG, 4); \
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EMIT_SIB64(PTR_SCALE, NA_TMP_REG, tab); /* mov tmp, [tab + tmp * {4,8}] */ \
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emith_lsr(func, a, SH2_WRITE_SHIFT); /* tmp = a >> WRT_SHIFT */ \
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EMIT_REX_IF(1, func, tab); \
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EMIT_OP_MODRM64(0x8b, 0, func, 4); \
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EMIT_SIB64(PTR_SCALE, func, tab); /* mov tmp, [tab + tmp * {4,8}] */ \
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emith_move_r_r_ptr(arg2_, CONTEXT_REG); \
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emith_jump_reg(NA_TMP_REG); \
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emith_jump_reg(func); \
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}
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#define emith_sh2_dtbf_loop() { \
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@ -328,7 +328,7 @@ struct block_list {
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static struct block_list **inval_lookup[TCACHE_BUFFERS];
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static const int hash_table_sizes[TCACHE_BUFFERS] = {
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0x1000,
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0x4000,
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0x100,
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0x100,
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};
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@ -498,12 +498,12 @@ static void (*sh2_drc_dispatcher)(void);
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static void (*sh2_drc_exit)(void);
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static void (*sh2_drc_test_irq)(void);
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static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
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static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
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static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
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static u32 REGPARM(1) (*sh2_drc_read8)(u32 a);
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static u32 REGPARM(1) (*sh2_drc_read16)(u32 a);
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static u32 REGPARM(1) (*sh2_drc_read32)(u32 a);
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static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
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static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
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static void REGPARM(2) (*sh2_drc_write32)(u32 a, u32 d);
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// flags for memory access
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#define MF_SIZEMASK 0x03 // size of access
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@ -787,7 +787,7 @@ static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
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cnt = i + 1;
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if (cnt >= block_link_pool_max_counts[tcache_id]) {
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dbg(1, "bl overflow for tcache %d", tcache_id);
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return NULL;
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return sh2_drc_dispatcher;
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}
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bl += cnt;
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block_link_pool_counts[tcache_id]++;
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@ -848,7 +848,7 @@ static void dr_link_blocks(struct block_entry *be, int tcache_id)
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dbg(1, "warning: " #array " overflow"); \
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failcode; \
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} else \
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array[count++] = item; \
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array[count++] = item; \
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}
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static int find_in_array(u32 *array, size_t size, u32 what)
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@ -1806,7 +1806,7 @@ static int emit_get_rbase_and_offs(SH2 *sh2, u32 a, u32 *offs)
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hr = rcache_get_tmp();
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if (mask < 0x1000) {
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// can't access data array or BIOS directly from ROM or SDRAM,
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// since code may run on both SH2s (if the tcache_id would be known...)
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// since code may run on both SH2s (tcache_id of translation block needed))
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emith_ctx_read(hr, poffs);
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if (a & mask & ~omask)
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emith_add_r_imm(hr, a & mask & ~omask);
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@ -1896,8 +1896,6 @@ static void emit_or_t_if_eq(int srr)
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// rd = @(arg0)
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static int emit_memhandler_read(int size)
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{
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int arg1;
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rcache_clean_tmp();
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#ifndef DRC_SR_REG
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// must writeback cycles for poll detection stuff
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@ -1905,8 +1903,6 @@ static int emit_memhandler_read(int size)
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rcache_evict_vreg(guest_regs[SHR_SR].vreg);
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#endif
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arg1 = rcache_get_tmp_arg(1);
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emith_move_r_r_ptr(arg1, CONTEXT_REG);
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switch (size & MF_SIZEMASK) {
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case 0: emith_call(sh2_drc_read8); break; // 8
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case 1: emith_call(sh2_drc_read16); break; // 16
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@ -1920,16 +1916,12 @@ static int emit_memhandler_read(int size)
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// @(arg0) = arg1
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static void emit_memhandler_write(int size)
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{
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int arg2;
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rcache_clean_tmp();
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#ifndef DRC_SR_REG
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if (guest_regs[SHR_SR].vreg != -1)
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rcache_evict_vreg(guest_regs[SHR_SR].vreg);
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#endif
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arg2 = rcache_get_tmp_arg(2);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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switch (size & MF_SIZEMASK) {
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case 0: emith_call(sh2_drc_write8); break; // 8
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case 1: emith_call(sh2_drc_write16); break; // 16
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@ -2372,7 +2364,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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rcache_unlock_all();
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#if (DRC_DEBUG & (8|256|512|1024))
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emit_move_r_imm32(SHR_PC, pc);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL);
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FLUSH_CYCLES(sr);
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rcache_clean();
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@ -2392,7 +2383,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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#ifdef DRC_CMP
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if (!(op_flags[i] & OF_DELAY_OP)) {
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emit_move_r_imm32(SHR_PC, pc);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL);
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FLUSH_CYCLES(sr);
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rcache_clean();
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@ -3666,16 +3656,69 @@ end_op:
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static void sh2_generate_utils(void)
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{
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int arg0, arg1, arg2, sr, tmp;
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sh2_drc_read8 = p32x_sh2_read8;
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sh2_drc_read16 = p32x_sh2_read16;
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sh2_drc_read32 = p32x_sh2_read32;
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int arg0, arg1, arg2, arg3, sr, tmp;
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host_arg2reg(arg0, 0);
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host_arg2reg(arg1, 1);
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host_arg2reg(arg2, 2);
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host_arg2reg(arg3, 3);
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emith_move_r_r(arg0, arg0); // nop
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emith_move_r_r(arg1, arg1); // nop
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emith_move_r_r(arg2, arg2); // nop
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emith_move_r_r(arg3, arg3); // nop
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// sh2_drc_write8(u32 a, u32 d)
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sh2_drc_write8 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write8_tab));
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emith_sh2_wcall(arg0, arg1, arg2, arg3);
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// sh2_drc_write16(u32 a, u32 d)
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sh2_drc_write16 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write16_tab));
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emith_sh2_wcall(arg0, arg1, arg2, arg3);
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// sh2_drc_write32(u32 a, u32 d)
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sh2_drc_write32 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write32_tab));
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emith_sh2_wcall(arg0, arg1, arg2, arg3);
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||||
|
||||
// d = sh2_drc_read8(u32 a)
|
||||
sh2_drc_read8 = (void *)tcache_ptr;
|
||||
emith_ctx_read_ptr(arg1, offsetof(SH2, read8_map));
|
||||
emith_sh2_rcall(arg0, arg1, arg2, arg3);
|
||||
EMITH_SJMP_START(DCOND_CS);
|
||||
emith_and_r_r_c(DCOND_CC, arg0, arg3);
|
||||
emith_eor_r_imm_c(DCOND_CC, arg0, 1);
|
||||
emith_read8_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
|
||||
emith_ret_c(DCOND_CC);
|
||||
EMITH_SJMP_END(DCOND_CS);
|
||||
emith_move_r_r_ptr(arg1, CONTEXT_REG);
|
||||
emith_jump_reg(arg2);
|
||||
|
||||
// d = sh2_drc_read16(u32 a)
|
||||
sh2_drc_read16 = (void *)tcache_ptr;
|
||||
emith_ctx_read_ptr(arg1, offsetof(SH2, read16_map));
|
||||
emith_sh2_rcall(arg0, arg1, arg2, arg3);
|
||||
EMITH_SJMP_START(DCOND_CS);
|
||||
emith_and_r_r_c(DCOND_CC, arg0, arg3);
|
||||
emith_read16_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
|
||||
emith_ret_c(DCOND_CC);
|
||||
EMITH_SJMP_END(DCOND_CS);
|
||||
emith_move_r_r_ptr(arg1, CONTEXT_REG);
|
||||
emith_jump_reg(arg2);
|
||||
|
||||
// d = sh2_drc_read32(u32 a)
|
||||
sh2_drc_read32 = (void *)tcache_ptr;
|
||||
emith_ctx_read_ptr(arg1, offsetof(SH2, read32_map));
|
||||
emith_sh2_rcall(arg0, arg1, arg2, arg3);
|
||||
EMITH_SJMP_START(DCOND_CS);
|
||||
emith_and_r_r_c(DCOND_CC, arg0, arg3);
|
||||
emith_read_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
|
||||
emith_ror_c(DCOND_CC, RET_REG, RET_REG, 16);
|
||||
emith_ret_c(DCOND_CC);
|
||||
EMITH_SJMP_END(DCOND_CS);
|
||||
emith_move_r_r_ptr(arg1, CONTEXT_REG);
|
||||
emith_jump_reg(arg2);
|
||||
|
||||
// sh2_drc_exit(void)
|
||||
sh2_drc_exit = (void *)tcache_ptr;
|
||||
|
|
@ -3766,21 +3809,6 @@ static void sh2_generate_utils(void)
|
|||
emith_call(sh2_drc_test_irq);
|
||||
emith_jump(sh2_drc_dispatcher);
|
||||
|
||||
// sh2_drc_write8(u32 a, u32 d)
|
||||
sh2_drc_write8 = (void *)tcache_ptr;
|
||||
emith_ctx_read_ptr(arg2, offsetof(SH2, write8_tab));
|
||||
emith_sh2_wcall(arg0, arg2);
|
||||
|
||||
// sh2_drc_write16(u32 a, u32 d)
|
||||
sh2_drc_write16 = (void *)tcache_ptr;
|
||||
emith_ctx_read_ptr(arg2, offsetof(SH2, write16_tab));
|
||||
emith_sh2_wcall(arg0, arg2);
|
||||
|
||||
// sh2_drc_write32(u32 a, u32 d)
|
||||
sh2_drc_write32 = (void *)tcache_ptr;
|
||||
emith_ctx_read_ptr(arg2, offsetof(SH2, write32_tab));
|
||||
emith_sh2_wcall(arg0, arg2);
|
||||
|
||||
#ifdef PDB_NET
|
||||
// debug
|
||||
#define MAKE_READ_WRAPPER(func) { \
|
||||
|
|
@ -3815,11 +3843,6 @@ static void sh2_generate_utils(void)
|
|||
MAKE_WRITE_WRAPPER(sh2_drc_write8);
|
||||
MAKE_WRITE_WRAPPER(sh2_drc_write16);
|
||||
MAKE_WRITE_WRAPPER(sh2_drc_write32);
|
||||
#if (DRC_DEBUG & 4)
|
||||
host_dasm_new_symbol(sh2_drc_read8);
|
||||
host_dasm_new_symbol(sh2_drc_read16);
|
||||
host_dasm_new_symbol(sh2_drc_read32);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
rcache_invalidate();
|
||||
|
|
@ -3831,6 +3854,9 @@ static void sh2_generate_utils(void)
|
|||
host_dasm_new_symbol(sh2_drc_write8);
|
||||
host_dasm_new_symbol(sh2_drc_write16);
|
||||
host_dasm_new_symbol(sh2_drc_write32);
|
||||
host_dasm_new_symbol(sh2_drc_read8);
|
||||
host_dasm_new_symbol(sh2_drc_read16);
|
||||
host_dasm_new_symbol(sh2_drc_read32);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -3955,14 +3981,15 @@ static void sh2_smc_rm_blocks(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift,
|
|||
}
|
||||
}
|
||||
|
||||
void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
|
||||
void sh2_drc_wcheck_ram(unsigned int a, int val, SH2 *sh2)
|
||||
{
|
||||
dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
|
||||
dbg(2, "%csh2 smc check @%08x", sh2->is_slave ? 's' : 'm', a);
|
||||
sh2_smc_rm_blocks(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
|
||||
}
|
||||
|
||||
void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
|
||||
void sh2_drc_wcheck_da(unsigned int a, int val, SH2 *sh2)
|
||||
{
|
||||
int cpuid = sh2->is_slave;
|
||||
dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
|
||||
sh2_smc_rm_blocks(a, Pico32xMem->drcblk_da[cpuid],
|
||||
1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
|
||||
|
|
@ -4051,6 +4078,9 @@ void sh2_drc_mem_setup(SH2 *sh2)
|
|||
sh2->p_da = sh2->data_array;
|
||||
sh2->p_sdram = Pico32xMem->sdram;
|
||||
sh2->p_rom = Pico.rom;
|
||||
// sh2->p_dram filled in dram bank switching
|
||||
sh2->p_drcblk_da = Pico32xMem->drcblk_da[!!sh2->is_slave];
|
||||
sh2->p_drcblk_ram = Pico32xMem->drcblk_ram;
|
||||
}
|
||||
|
||||
void sh2_drc_frame(void)
|
||||
|
|
@ -4103,6 +4133,7 @@ int sh2_drc_init(SH2 *sh2)
|
|||
// disasm the utils
|
||||
tcache_dsm_ptrs[0] = tcache;
|
||||
do_host_disasm(0);
|
||||
fflush(stdout);
|
||||
#endif
|
||||
#if (DRC_DEBUG & 1)
|
||||
hash_collisions = 0;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
int sh2_drc_init(SH2 *sh2);
|
||||
void sh2_drc_finish(SH2 *sh2);
|
||||
void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid);
|
||||
void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid);
|
||||
void sh2_drc_wcheck_ram(unsigned int a, int val, SH2 *sh2);
|
||||
void sh2_drc_wcheck_da(unsigned int a, int val, SH2 *sh2);
|
||||
|
||||
#ifdef DRC_SH2
|
||||
void sh2_drc_mem_setup(SH2 *sh2);
|
||||
|
|
|
|||
|
|
@ -36,6 +36,9 @@ typedef struct SH2_
|
|||
void *p_da;
|
||||
void *p_sdram;
|
||||
void *p_rom;
|
||||
void *p_dram;
|
||||
void *p_drcblk_da;
|
||||
void *p_drcblk_ram;
|
||||
unsigned int pdb_io_csum[2];
|
||||
|
||||
#define SH2_STATE_RUN (1 << 0) // to prevent recursion
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue