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https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
sh2 memory interface optimzations
This commit is contained in:
kub
parent
4f4e9bf3bd
commit
6822ba9d64
10 changed files with 585 additions and 157 deletions
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@ -328,7 +328,7 @@ struct block_list {
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static struct block_list **inval_lookup[TCACHE_BUFFERS];
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static const int hash_table_sizes[TCACHE_BUFFERS] = {
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0x1000,
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0x4000,
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0x100,
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0x100,
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};
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@ -498,12 +498,12 @@ static void (*sh2_drc_dispatcher)(void);
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static void (*sh2_drc_exit)(void);
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static void (*sh2_drc_test_irq)(void);
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static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
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static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
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static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
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static u32 REGPARM(1) (*sh2_drc_read8)(u32 a);
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static u32 REGPARM(1) (*sh2_drc_read16)(u32 a);
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static u32 REGPARM(1) (*sh2_drc_read32)(u32 a);
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static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
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static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
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static void REGPARM(2) (*sh2_drc_write32)(u32 a, u32 d);
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// flags for memory access
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#define MF_SIZEMASK 0x03 // size of access
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@ -787,7 +787,7 @@ static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
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cnt = i + 1;
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if (cnt >= block_link_pool_max_counts[tcache_id]) {
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dbg(1, "bl overflow for tcache %d", tcache_id);
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return NULL;
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return sh2_drc_dispatcher;
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}
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bl += cnt;
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block_link_pool_counts[tcache_id]++;
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@ -848,7 +848,7 @@ static void dr_link_blocks(struct block_entry *be, int tcache_id)
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dbg(1, "warning: " #array " overflow"); \
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failcode; \
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} else \
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array[count++] = item; \
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array[count++] = item; \
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}
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static int find_in_array(u32 *array, size_t size, u32 what)
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@ -1806,7 +1806,7 @@ static int emit_get_rbase_and_offs(SH2 *sh2, u32 a, u32 *offs)
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hr = rcache_get_tmp();
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if (mask < 0x1000) {
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// can't access data array or BIOS directly from ROM or SDRAM,
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// since code may run on both SH2s (if the tcache_id would be known...)
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// since code may run on both SH2s (tcache_id of translation block needed))
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emith_ctx_read(hr, poffs);
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if (a & mask & ~omask)
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emith_add_r_imm(hr, a & mask & ~omask);
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@ -1896,8 +1896,6 @@ static void emit_or_t_if_eq(int srr)
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// rd = @(arg0)
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static int emit_memhandler_read(int size)
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{
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int arg1;
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rcache_clean_tmp();
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#ifndef DRC_SR_REG
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// must writeback cycles for poll detection stuff
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@ -1905,8 +1903,6 @@ static int emit_memhandler_read(int size)
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rcache_evict_vreg(guest_regs[SHR_SR].vreg);
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#endif
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arg1 = rcache_get_tmp_arg(1);
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emith_move_r_r_ptr(arg1, CONTEXT_REG);
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switch (size & MF_SIZEMASK) {
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case 0: emith_call(sh2_drc_read8); break; // 8
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case 1: emith_call(sh2_drc_read16); break; // 16
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@ -1920,16 +1916,12 @@ static int emit_memhandler_read(int size)
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// @(arg0) = arg1
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static void emit_memhandler_write(int size)
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{
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int arg2;
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rcache_clean_tmp();
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#ifndef DRC_SR_REG
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if (guest_regs[SHR_SR].vreg != -1)
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rcache_evict_vreg(guest_regs[SHR_SR].vreg);
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#endif
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arg2 = rcache_get_tmp_arg(2);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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switch (size & MF_SIZEMASK) {
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case 0: emith_call(sh2_drc_write8); break; // 8
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case 1: emith_call(sh2_drc_write16); break; // 16
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@ -2372,7 +2364,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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rcache_unlock_all();
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#if (DRC_DEBUG & (8|256|512|1024))
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emit_move_r_imm32(SHR_PC, pc);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL);
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FLUSH_CYCLES(sr);
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rcache_clean();
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@ -2392,7 +2383,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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#ifdef DRC_CMP
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if (!(op_flags[i] & OF_DELAY_OP)) {
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emit_move_r_imm32(SHR_PC, pc);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL);
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FLUSH_CYCLES(sr);
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rcache_clean();
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@ -3666,16 +3656,69 @@ end_op:
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static void sh2_generate_utils(void)
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{
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int arg0, arg1, arg2, sr, tmp;
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sh2_drc_read8 = p32x_sh2_read8;
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sh2_drc_read16 = p32x_sh2_read16;
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sh2_drc_read32 = p32x_sh2_read32;
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int arg0, arg1, arg2, arg3, sr, tmp;
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host_arg2reg(arg0, 0);
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host_arg2reg(arg1, 1);
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host_arg2reg(arg2, 2);
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host_arg2reg(arg3, 3);
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emith_move_r_r(arg0, arg0); // nop
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emith_move_r_r(arg1, arg1); // nop
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emith_move_r_r(arg2, arg2); // nop
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emith_move_r_r(arg3, arg3); // nop
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// sh2_drc_write8(u32 a, u32 d)
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sh2_drc_write8 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write8_tab));
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emith_sh2_wcall(arg0, arg1, arg2, arg3);
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// sh2_drc_write16(u32 a, u32 d)
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sh2_drc_write16 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write16_tab));
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emith_sh2_wcall(arg0, arg1, arg2, arg3);
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// sh2_drc_write32(u32 a, u32 d)
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sh2_drc_write32 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write32_tab));
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emith_sh2_wcall(arg0, arg1, arg2, arg3);
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// d = sh2_drc_read8(u32 a)
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sh2_drc_read8 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg1, offsetof(SH2, read8_map));
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emith_sh2_rcall(arg0, arg1, arg2, arg3);
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EMITH_SJMP_START(DCOND_CS);
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emith_and_r_r_c(DCOND_CC, arg0, arg3);
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emith_eor_r_imm_c(DCOND_CC, arg0, 1);
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emith_read8_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
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emith_ret_c(DCOND_CC);
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EMITH_SJMP_END(DCOND_CS);
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emith_move_r_r_ptr(arg1, CONTEXT_REG);
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emith_jump_reg(arg2);
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// d = sh2_drc_read16(u32 a)
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sh2_drc_read16 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg1, offsetof(SH2, read16_map));
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emith_sh2_rcall(arg0, arg1, arg2, arg3);
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EMITH_SJMP_START(DCOND_CS);
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emith_and_r_r_c(DCOND_CC, arg0, arg3);
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emith_read16_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
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emith_ret_c(DCOND_CC);
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EMITH_SJMP_END(DCOND_CS);
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emith_move_r_r_ptr(arg1, CONTEXT_REG);
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emith_jump_reg(arg2);
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// d = sh2_drc_read32(u32 a)
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sh2_drc_read32 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg1, offsetof(SH2, read32_map));
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emith_sh2_rcall(arg0, arg1, arg2, arg3);
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EMITH_SJMP_START(DCOND_CS);
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emith_and_r_r_c(DCOND_CC, arg0, arg3);
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emith_read_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
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emith_ror_c(DCOND_CC, RET_REG, RET_REG, 16);
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emith_ret_c(DCOND_CC);
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EMITH_SJMP_END(DCOND_CS);
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emith_move_r_r_ptr(arg1, CONTEXT_REG);
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emith_jump_reg(arg2);
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// sh2_drc_exit(void)
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sh2_drc_exit = (void *)tcache_ptr;
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@ -3766,21 +3809,6 @@ static void sh2_generate_utils(void)
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emith_call(sh2_drc_test_irq);
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emith_jump(sh2_drc_dispatcher);
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// sh2_drc_write8(u32 a, u32 d)
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sh2_drc_write8 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write8_tab));
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emith_sh2_wcall(arg0, arg2);
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// sh2_drc_write16(u32 a, u32 d)
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sh2_drc_write16 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write16_tab));
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emith_sh2_wcall(arg0, arg2);
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// sh2_drc_write32(u32 a, u32 d)
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sh2_drc_write32 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write32_tab));
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emith_sh2_wcall(arg0, arg2);
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#ifdef PDB_NET
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// debug
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#define MAKE_READ_WRAPPER(func) { \
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@ -3815,11 +3843,6 @@ static void sh2_generate_utils(void)
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MAKE_WRITE_WRAPPER(sh2_drc_write8);
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MAKE_WRITE_WRAPPER(sh2_drc_write16);
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MAKE_WRITE_WRAPPER(sh2_drc_write32);
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#if (DRC_DEBUG & 4)
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host_dasm_new_symbol(sh2_drc_read8);
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host_dasm_new_symbol(sh2_drc_read16);
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host_dasm_new_symbol(sh2_drc_read32);
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#endif
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#endif
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rcache_invalidate();
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@ -3831,6 +3854,9 @@ static void sh2_generate_utils(void)
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host_dasm_new_symbol(sh2_drc_write8);
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host_dasm_new_symbol(sh2_drc_write16);
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host_dasm_new_symbol(sh2_drc_write32);
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host_dasm_new_symbol(sh2_drc_read8);
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host_dasm_new_symbol(sh2_drc_read16);
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host_dasm_new_symbol(sh2_drc_read32);
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#endif
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}
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@ -3955,14 +3981,15 @@ static void sh2_smc_rm_blocks(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift,
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}
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}
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void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
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void sh2_drc_wcheck_ram(unsigned int a, int val, SH2 *sh2)
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{
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dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
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dbg(2, "%csh2 smc check @%08x", sh2->is_slave ? 's' : 'm', a);
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sh2_smc_rm_blocks(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
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}
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void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
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void sh2_drc_wcheck_da(unsigned int a, int val, SH2 *sh2)
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{
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int cpuid = sh2->is_slave;
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dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
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sh2_smc_rm_blocks(a, Pico32xMem->drcblk_da[cpuid],
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1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
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@ -4051,6 +4078,9 @@ void sh2_drc_mem_setup(SH2 *sh2)
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sh2->p_da = sh2->data_array;
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sh2->p_sdram = Pico32xMem->sdram;
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sh2->p_rom = Pico.rom;
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// sh2->p_dram filled in dram bank switching
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sh2->p_drcblk_da = Pico32xMem->drcblk_da[!!sh2->is_slave];
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sh2->p_drcblk_ram = Pico32xMem->drcblk_ram;
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}
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void sh2_drc_frame(void)
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@ -4103,6 +4133,7 @@ int sh2_drc_init(SH2 *sh2)
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// disasm the utils
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tcache_dsm_ptrs[0] = tcache;
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do_host_disasm(0);
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fflush(stdout);
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#endif
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#if (DRC_DEBUG & 1)
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hash_collisions = 0;
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