mirror of
https://github.com/RaySollium99/picodrive.git
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sh2 memory interface optimzations
This commit is contained in:
kub
parent
4f4e9bf3bd
commit
6822ba9d64
10 changed files with 585 additions and 157 deletions
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@ -1066,41 +1066,41 @@ void PicoWrite16_32x(u32 a, u32 d)
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}
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/* quirk: in both normal and overwrite areas only nonzero values go through */
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#define sh2_write8_dramN(n) \
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#define sh2_write8_dramN(p, a, d) \
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if ((d & 0xff) != 0) { \
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u8 *dram = (u8 *)Pico32xMem->dram[n]; \
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u8 *dram = (u8 *)p; \
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dram[(a & 0x1ffff) ^ 1] = d; \
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}
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static void m68k_write8_dram0_ow(u32 a, u32 d)
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{
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sh2_write8_dramN(0);
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sh2_write8_dramN(Pico32xMem->dram[0], a, d);
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}
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static void m68k_write8_dram1_ow(u32 a, u32 d)
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{
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sh2_write8_dramN(1);
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sh2_write8_dramN(Pico32xMem->dram[1], a, d);
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}
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#define sh2_write16_dramN(n) \
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u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
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#define sh2_write16_dramN(p, a, d) \
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u16 *pd = &((u16 *)p)[(a & 0x1ffff) / 2]; \
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if (!(a & 0x20000)) { \
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*pd = d; \
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return; \
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} \
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/* overwrite */ \
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if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
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if (!(d & 0xff00)) d |= *pd & 0xff00; \
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*pd = d;
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} else { \
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u16 v = *pd; /* overwrite */ \
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if (!(d & 0x00ff)) d |= v & 0x00ff; \
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if (!(d & 0xff00)) d |= v & 0xff00; \
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*pd = d; \
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}
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static void m68k_write16_dram0_ow(u32 a, u32 d)
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{
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sh2_write16_dramN(0);
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sh2_write16_dramN(Pico32xMem->dram[0], a, d);
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}
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static void m68k_write16_dram1_ow(u32 a, u32 d)
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{
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sh2_write16_dramN(1);
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sh2_write16_dramN(Pico32xMem->dram[1], a, d);
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}
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// -----------------------------------------------------------------
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@ -1229,14 +1229,14 @@ static void bank_switch_rom_68k(int b)
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// -----------------------------------------------------------------
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// read8
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static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
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static REGPARM(2) u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
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{
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elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
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a, 0, sh2_pc(sh2));
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return 0;
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}
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static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read8_cs0(u32 a, SH2 *sh2)
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{
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u32 d = 0;
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DRC_SAVE_SR(sh2);
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@ -1282,27 +1282,28 @@ out:
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return d;
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}
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static u32 sh2_read8_da(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read8_da(u32 a, SH2 *sh2)
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{
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return sh2->data_array[(a & 0xfff) ^ 1];
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}
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// for ssf2
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static u32 sh2_read8_rom(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read8_rom(u32 a, SH2 *sh2)
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{
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u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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return Pico.rom[(bank + (a & 0x7ffff)) ^ 1];
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u8 *p = sh2->p_rom;
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return p[(bank + (a & 0x7ffff)) ^ 1];
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}
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// read16
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static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read16_unmapped(u32 a, SH2 *sh2)
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{
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elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
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a, 0, sh2_pc(sh2));
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return 0;
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}
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static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read16_cs0(u32 a, SH2 *sh2)
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{
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u32 d = 0;
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DRC_SAVE_SR(sh2);
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@ -1342,39 +1343,41 @@ out_noprint:
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return d;
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}
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static u32 sh2_read16_da(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read16_da(u32 a, SH2 *sh2)
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{
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return ((u16 *)sh2->data_array)[(a & 0xffe) / 2];
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}
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static u32 sh2_read16_rom(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read16_rom(u32 a, SH2 *sh2)
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{
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u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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return *(u16 *)(Pico.rom + bank + (a & 0x7fffe));
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u16 *p = sh2->p_rom;
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return p[(bank + (a & 0x7fffe)) / 2];
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}
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static u32 sh2_read32_unmapped(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read32_unmapped(u32 a, SH2 *sh2)
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{
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elprintf_sh2(sh2, EL_32X, "unmapped r32 [%08x] %08x @%06x",
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a, 0, sh2_pc(sh2));
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return 0;
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}
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static u32 sh2_read32_cs0(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read32_cs0(u32 a, SH2 *sh2)
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{
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return (sh2_read16_cs0(a, sh2) << 16) | sh2_read16_cs0(a + 2, sh2);
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}
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static u32 sh2_read32_da(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read32_da(u32 a, SH2 *sh2)
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{
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u32 d = *((u32 *)sh2->data_array + (a & 0xffc)/4);
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return (d << 16) | (d >> 16);
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}
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static u32 sh2_read32_rom(u32 a, SH2 *sh2)
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static u32 REGPARM(2) sh2_read32_rom(u32 a, SH2 *sh2)
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{
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u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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u32 d = *(u32 *)(Pico.rom + bank + (a & 0x7fffc));
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u32 *p = sh2->p_rom;
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u32 d = p[(bank + (a & 0x7fffc)) / 4];
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return (d << 16) | (d >> 16);
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}
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@ -1420,25 +1423,21 @@ out:
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DRC_RESTORE_SR(sh2);
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}
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static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write8_dram(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write8_dramN(0);
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}
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static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write8_dramN(1);
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sh2_write8_dramN(sh2->p_dram, a, d);
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}
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static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3ffff;
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#ifdef DRC_SH2
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int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
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u16 *p = sh2->p_drcblk_ram;
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int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (t)
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sh2_drc_wcheck_ram(a, t, sh2->is_slave);
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sh2_drc_wcheck_ram(a, t, sh2);
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#endif
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Pico32xMem->sdram[a1 ^ 1] = d;
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((u8 *)sh2->p_sdram)[a1 ^ 1] = d;
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}
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static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
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@ -1457,10 +1456,10 @@ static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xfff;
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#ifdef DRC_SH2
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int id = sh2->is_slave;
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int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
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u16 *p = sh2->p_drcblk_da;
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int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
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if (t)
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sh2_drc_wcheck_da(a, t, id);
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sh2_drc_wcheck_da(a, t, sh2);
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#endif
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sh2->data_array[a1 ^ 1] = d;
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}
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@ -1503,42 +1502,38 @@ out:
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DRC_RESTORE_SR(sh2);
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}
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static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write16_dram(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write16_dramN(0);
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}
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static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write16_dramN(1);
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sh2_write16_dramN(sh2->p_dram, a, d);
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}
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static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3ffff;
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u32 a1 = a & 0x3fffe;
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#ifdef DRC_SH2
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int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
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u16 *p = sh2->p_drcblk_ram;
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int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (t)
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sh2_drc_wcheck_ram(a, t, sh2->is_slave);
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sh2_drc_wcheck_ram(a, t, sh2);
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#endif
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((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
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((u16 *)sh2->p_sdram)[a1 / 2] = d;
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}
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static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xfff;
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u32 a1 = a & 0xffe;
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#ifdef DRC_SH2
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int id = sh2->is_slave;
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int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
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u16 *p = sh2->p_drcblk_da;
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int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
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if (t)
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sh2_drc_wcheck_da(a, t, id);
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sh2_drc_wcheck_da(a, t, sh2);
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#endif
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((u16 *)sh2->data_array)[a1 / 2] = d;
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}
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static void REGPARM(3) sh2_write16_rom(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3fffff;
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u32 a1 = a & 0x3ffffe;
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// tweak for WWF Raw: does writes to ROM area, and it doesn't work without
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// allowing this.
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// Presumably the write goes to the CPU cache and is read back from there,
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@ -1562,54 +1557,53 @@ static void REGPARM(3) sh2_write32_cs0(u32 a, u32 d, SH2 *sh2)
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sh2_write16_cs0(a + 2, d, sh2);
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}
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#define sh2_write32_dramN(n) \
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u32 *pd = (u32 *)&Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
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#define sh2_write32_dramN(p, a, d) \
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u32 *pd = &((u32 *)p)[(a & 0x1ffff) / 4]; \
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if (!(a & 0x20000)) { \
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*pd = (d << 16) | (d >> 16); \
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return; \
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} \
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/* overwrite */ \
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u8 *pb = (u8 *)pd; \
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if (d & 0x000000ff) pb[2] = d; \
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if (d & 0x0000ff00) pb[3] = d >> 8; \
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if (d & 0x00ff0000) pb[0] = d >> 16; \
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if (d & 0xff000000) pb[1] = d >> 24; \
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} else { \
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/* overwrite */ \
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u32 v = *pd, m = 0; d = (d << 16) | (d >> 16) ; \
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if (!(d & 0x000000ff)) m |= 0x000000ff; \
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if (!(d & 0x0000ff00)) m |= 0x0000ff00; \
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if (!(d & 0x00ff0000)) m |= 0x00ff0000; \
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if (!(d & 0xff000000)) m |= 0xff000000; \
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*pd = d | (v&m); \
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}
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static void REGPARM(3) sh2_write32_dram0(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write32_dram(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write32_dramN(0);
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}
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static void REGPARM(3) sh2_write32_dram1(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write32_dramN(1);
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sh2_write32_dramN(sh2->p_dram, a, d);
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}
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static void REGPARM(3) sh2_write32_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3fffc;
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*(u32 *)(sh2->p_sdram + a1) = (d << 16) | (d >> 16);
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#ifdef DRC_SH2
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unsigned short *p = &Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (p[0])
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sh2_drc_wcheck_ram(a, p[0], sh2->is_slave);
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if (p[1])
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sh2_drc_wcheck_ram(a+2, p[1], sh2->is_slave);
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u16 *p = sh2->p_drcblk_ram;
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int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (t)
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sh2_drc_wcheck_ram(a, t, sh2);
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int u = p[(a1+2) >> SH2_DRCBLK_RAM_SHIFT];
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if (u)
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sh2_drc_wcheck_ram(a+2, u, sh2);
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#endif
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*(u32 *)(sh2->p_sdram + a1) = (d << 16) | (d >> 16);
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}
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static void REGPARM(3) sh2_write32_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xffc;
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*((u32 *)sh2->data_array + a1/4) = (d << 16) | (d >> 16);
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#ifdef DRC_SH2
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int id = sh2->is_slave;
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unsigned short *p = &Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
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if (p[0])
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sh2_drc_wcheck_da(a, p[0], id);
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if (p[1])
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sh2_drc_wcheck_da(a+2, p[1], id);
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u16 *p = sh2->p_drcblk_da;
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int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
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if (t)
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sh2_drc_wcheck_da(a, t, sh2);
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int u = p[(a1+2) >> SH2_DRCBLK_DA_SHIFT];
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if (u)
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sh2_drc_wcheck_da(a+2, u, sh2);
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#endif
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*((u32 *)sh2->data_array + a1/4) = (d << 16) | (d >> 16);
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}
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static void REGPARM(3) sh2_write32_rom(u32 a, u32 d, SH2 *sh2)
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@ -1919,9 +1913,7 @@ void Pico32xSwapDRAM(int b)
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sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr =
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sh2_read32_map[0x04/2].addr = sh2_read32_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
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sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
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sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
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sh2_write32_map[0x04/2] = sh2_write32_map[0x24/2] = b ? sh2_write32_dram1 : sh2_write32_dram0;
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msh2.p_dram = ssh2.p_dram = Pico32xMem->dram[b]; // DRC conveniance ptr
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}
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static void bank_switch_rom_sh2(void)
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@ -2035,10 +2027,14 @@ void PicoMemSetup32x(void)
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sh2_read32_map[0x02/2].mask = sh2_read32_map[0x22/2].mask = 0x3ffffc; // FIXME
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sh2_write16_map[0x02/2] = sh2_write16_map[0x22/2] = sh2_write16_rom;
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sh2_write32_map[0x02/2] = sh2_write32_map[0x22/2] = sh2_write32_rom;
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// CS2 - DRAM - done by Pico32xSwapDRAM()
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// CS2 - DRAM
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sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask = 0x01ffff;
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sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01fffe;
|
||||
sh2_read32_map[0x04/2].mask = sh2_read32_map[0x24/2].mask = 0x01fffc;
|
||||
sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = sh2_write8_dram;
|
||||
sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = sh2_write16_dram;
|
||||
sh2_write32_map[0x04/2] = sh2_write32_map[0x24/2] = sh2_write32_dram;
|
||||
|
||||
// CS3 - SDRAM
|
||||
sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
|
||||
sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr =
|
||||
|
|
|
|||
305
pico/32x/memory_arm.S
Normal file
305
pico/32x/memory_arm.S
Normal file
|
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* PicoDrive 32X memory access functions, assembler version
|
||||
* (C) KUB, 2018
|
||||
*
|
||||
* This work is licensed under the terms of MAME license.
|
||||
* See COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#include "../pico_int_o32.h"
|
||||
|
||||
@ 32X bank sizes... TODO this should somehow come from an include file
|
||||
.equ SH2_ROM_SHIFT, 10 @ 0x003fffff
|
||||
.equ SH2_RAM_SHIFT, 14 @ 0x0003ffff
|
||||
.equ SH2_DRAM_SHIFT,15 @ 0x0001ffff
|
||||
.equ SH2_DA_SHIFT, 20 @ 0x00000fff
|
||||
|
||||
.equ SH2_DRAM_OW, 1<<(32-SH2_DRAM_SHIFT) @ DRAM overwrite mode bit
|
||||
|
||||
.text
|
||||
|
||||
@ u32 a
|
||||
.global sh2_read8_rom
|
||||
.global sh2_read8_sdram
|
||||
.global sh2_read8_da
|
||||
.global sh2_read8_dram
|
||||
.global sh2_read16_rom
|
||||
.global sh2_read16_sdram
|
||||
.global sh2_read16_da
|
||||
.global sh2_read16_dram
|
||||
.global sh2_read32_rom
|
||||
.global sh2_read32_sdram
|
||||
.global sh2_read32_da
|
||||
.global sh2_read32_dram
|
||||
|
||||
@ u32 a, u32 d
|
||||
.global sh2_write8_sdram
|
||||
.global sh2_write8_da
|
||||
.global sh2_write8_dram
|
||||
.global sh2_write16_sdram
|
||||
.global sh2_write16_da
|
||||
.global sh2_write16_dram
|
||||
.global sh2_write32_sdram
|
||||
.global sh2_write32_da
|
||||
.global sh2_write32_dram
|
||||
|
||||
sh2_read8_rom:
|
||||
ldr ip, [r1, #OFS_SH2_p_rom]
|
||||
eor r0, r0, #1
|
||||
lsl r0, #SH2_ROM_SHIFT
|
||||
ldrb r0, [ip, r0, lsr #SH2_ROM_SHIFT]
|
||||
bx lr
|
||||
|
||||
sh2_read8_sdram:
|
||||
ldr ip, [r1, #OFS_SH2_p_sdram]
|
||||
eor r0, r0, #1
|
||||
lsl r0, #SH2_RAM_SHIFT
|
||||
ldrb r0, [ip, r0, lsr #SH2_RAM_SHIFT]
|
||||
bx lr
|
||||
|
||||
sh2_read8_da:
|
||||
ldr ip, [r1, #OFS_SH2_p_da]
|
||||
eor r0, r0, #1
|
||||
lsl r0, #SH2_DA_SHIFT
|
||||
ldrb r0, [ip, r0, lsr #SH2_DA_SHIFT]
|
||||
bx lr
|
||||
|
||||
sh2_read8_dram:
|
||||
ldr ip, [r1, #OFS_SH2_p_dram]
|
||||
eor r0, r0, #1
|
||||
lsl r0, #SH2_DRAM_SHIFT
|
||||
ldrb r0, [ip, r0, lsr #SH2_DRAM_SHIFT]
|
||||
bx lr
|
||||
|
||||
sh2_read16_rom:
|
||||
ldr ip, [r1, #OFS_SH2_p_rom]
|
||||
lsl r0, #SH2_ROM_SHIFT
|
||||
lsr r0, #SH2_ROM_SHIFT
|
||||
ldrh r0, [ip, r0]
|
||||
bx lr
|
||||
|
||||
sh2_read16_sdram:
|
||||
ldr ip, [r1, #OFS_SH2_p_sdram]
|
||||
lsl r0, #SH2_RAM_SHIFT
|
||||
lsr r0, #SH2_RAM_SHIFT
|
||||
ldrh r0, [ip, r0]
|
||||
bx lr
|
||||
|
||||
sh2_read16_da:
|
||||
ldr ip, [r1, #OFS_SH2_p_da]
|
||||
lsl r0, #SH2_DA_SHIFT
|
||||
lsr r0, #SH2_DA_SHIFT
|
||||
ldrh r0, [ip, r0]
|
||||
bx lr
|
||||
|
||||
sh2_read16_dram:
|
||||
ldr ip, [r1, #OFS_SH2_p_dram]
|
||||
lsl r0, #SH2_DRAM_SHIFT
|
||||
lsr r0, #SH2_DRAM_SHIFT
|
||||
ldrh r0, [ip, r0]
|
||||
bx lr
|
||||
|
||||
sh2_read32_rom:
|
||||
ldr ip, [r1, #OFS_SH2_p_rom]
|
||||
lsl r0, #SH2_ROM_SHIFT
|
||||
ldr r0, [ip, r0, lsr #SH2_ROM_SHIFT]
|
||||
ror r0, r0, #16
|
||||
bx lr
|
||||
|
||||
sh2_read32_sdram:
|
||||
ldr ip, [r1, #OFS_SH2_p_sdram]
|
||||
lsl r0, #SH2_RAM_SHIFT
|
||||
ldr r0, [ip, r0, lsr #SH2_RAM_SHIFT]
|
||||
ror r0, r0, #16
|
||||
bx lr
|
||||
|
||||
sh2_read32_da:
|
||||
ldr ip, [r1, #OFS_SH2_p_da]
|
||||
lsl r0, #SH2_DA_SHIFT
|
||||
ldr r0, [ip, r0, lsr #SH2_DA_SHIFT]
|
||||
ror r0, r0, #16
|
||||
bx lr
|
||||
|
||||
sh2_read32_dram:
|
||||
ldr ip, [r1, #OFS_SH2_p_dram]
|
||||
lsl r0, #SH2_DRAM_SHIFT
|
||||
ldr r0, [ip, r0, lsr #SH2_DRAM_SHIFT]
|
||||
ror r0, r0, #16
|
||||
bx lr
|
||||
|
||||
sh2_write8_sdram:
|
||||
@ preserve r0 and r2 for tail call
|
||||
ldr ip, [r2, #OFS_SH2_p_sdram]
|
||||
eor r3, r0, #1
|
||||
lsl r3, #SH2_RAM_SHIFT
|
||||
strb r1, [ip, r3, lsr #SH2_RAM_SHIFT]
|
||||
#ifdef DRC_SH2
|
||||
ldr ip, [r2, #OFS_SH2_p_drcblk_ram]
|
||||
ldrb r1, [ip, r3, lsr #SH2_RAM_SHIFT+1]
|
||||
bic r0, r0, #1
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
b sh2_drc_wcheck_ram
|
||||
#else
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
sh2_write8_da:
|
||||
@ preserve r0 and r2 for tail call
|
||||
ldr ip, [r2, #OFS_SH2_p_da]
|
||||
eor r3, r0, #1
|
||||
lsl r3, #SH2_DA_SHIFT
|
||||
strb r1, [ip, r3, lsr #SH2_DA_SHIFT]
|
||||
#ifdef DRC_SH2
|
||||
ldr ip, [r2, #OFS_SH2_p_drcblk_da]
|
||||
ldrb r1, [ip, r3, lsr #SH2_DA_SHIFT+1]
|
||||
bic r0, r0, #1
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
b sh2_drc_wcheck_da
|
||||
#else
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
sh2_write8_dram:
|
||||
tst r1, #0xff
|
||||
ldrne ip, [r2, #OFS_SH2_p_dram]
|
||||
eorne r3, r0, #1
|
||||
lslne r3, #SH2_DRAM_SHIFT
|
||||
strneb r1, [ip, r3, lsr #SH2_DRAM_SHIFT]
|
||||
bx lr
|
||||
|
||||
sh2_write16_sdram:
|
||||
@ preserve r0 and r2 for tail call
|
||||
ldr ip, [r2, #OFS_SH2_p_sdram]
|
||||
lsl r3, r0, #SH2_RAM_SHIFT
|
||||
lsr r3, r3, #SH2_RAM_SHIFT
|
||||
strh r1, [ip, r3]
|
||||
#ifdef DRC_SH2
|
||||
ldr ip, [r2, #OFS_SH2_p_drcblk_ram]
|
||||
ldrb r1, [ip, r3, lsr #1]
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
b sh2_drc_wcheck_ram
|
||||
#else
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
sh2_write16_da:
|
||||
@ preserve r0 and r2 for tail call
|
||||
ldr ip, [r2, #OFS_SH2_p_da]
|
||||
lsl r3, r0, #SH2_DA_SHIFT
|
||||
lsr r3, r3, #SH2_DA_SHIFT
|
||||
strh r1, [ip, r3]
|
||||
#ifdef DRC_SH2
|
||||
ldr ip, [r2, #OFS_SH2_p_drcblk_da]
|
||||
ldrb r1, [ip, r3, lsr #1]
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
b sh2_drc_wcheck_da
|
||||
#else
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
sh2_write16_dram:
|
||||
ldr ip, [r2, #OFS_SH2_p_dram]
|
||||
tst r0, #SH2_DRAM_OW
|
||||
lsl r3, r0, #SH2_DRAM_SHIFT
|
||||
lsr r3, r3, #SH2_DRAM_SHIFT
|
||||
streqh r1, [ip, r3]
|
||||
bxeq lr
|
||||
add ip, ip, r3
|
||||
tst r1, #0xff
|
||||
strneb r1, [ip, #0]
|
||||
tst r1, #0xff00
|
||||
lsrne r1, r1, #8
|
||||
strneb r1, [ip, #1]
|
||||
bx lr
|
||||
|
||||
sh2_write32_sdram:
|
||||
@ preserve r0 and r2 for tail call
|
||||
ldr ip, [r2, #OFS_SH2_p_sdram]
|
||||
ror r1, r1, #16
|
||||
lsl r3, r0, #SH2_RAM_SHIFT
|
||||
str r1, [ip, r3, lsr #SH2_RAM_SHIFT]
|
||||
#ifdef DRC_SH2
|
||||
ldr ip, [r2, #OFS_SH2_p_drcblk_ram]
|
||||
ldrb r1, [ip, r3, lsr #SH2_RAM_SHIFT+1]!
|
||||
cmp r1, #0
|
||||
beq 1f
|
||||
stmfd sp!, {r0, r1, r2, ip}
|
||||
bl sh2_drc_wcheck_ram
|
||||
ldmfd sp!, {r0, r1, r2, ip}
|
||||
1: ldrb r1, [ip, #1]
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
add r0, r0, #2
|
||||
b sh2_drc_wcheck_ram
|
||||
#else
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
sh2_write32_da:
|
||||
@ preserve r0 and r2 for tail call
|
||||
ldr ip, [r2, #OFS_SH2_p_da]
|
||||
ror r1, r1, #16
|
||||
lsl r3, r0, #SH2_DA_SHIFT
|
||||
str r1, [ip, r3, lsr #SH2_DA_SHIFT]
|
||||
#ifdef DRC_SH2
|
||||
ldr ip, [r2, #OFS_SH2_p_drcblk_da]
|
||||
ldrb r1, [ip, r3, lsr #SH2_DA_SHIFT+1]!
|
||||
cmp r1, #0
|
||||
beq 1f
|
||||
stmfd sp!, {r0, r1, r2, ip}
|
||||
bl sh2_drc_wcheck_da
|
||||
ldmfd sp!, {r0, r1, r2, ip}
|
||||
1: ldrb r1, [ip, #1]
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
add r0, r0, #2
|
||||
b sh2_drc_wcheck_da
|
||||
#else
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
sh2_write32_dram:
|
||||
ldr ip, [r2, #OFS_SH2_p_dram]
|
||||
tst r0, #SH2_DRAM_OW
|
||||
lsl r3, r0, #SH2_DRAM_SHIFT
|
||||
roreq r1, r1, #16
|
||||
streq r1, [ip, r3, lsr #SH2_DRAM_SHIFT]
|
||||
bxeq lr
|
||||
#if 1
|
||||
ldr r0, [ip, r3, lsr #SH2_DRAM_SHIFT]
|
||||
ror r1, r1, #16
|
||||
mov r2, #0
|
||||
tst r1, #0x00ff0000
|
||||
orrne r2, r2, #0x00ff0000
|
||||
tst r1, #0xff000000
|
||||
orrne r2, r2, #0xff000000
|
||||
tst r1, #0x000000ff
|
||||
orrne r2, r2, #0x000000ff
|
||||
tst r1, #0x0000ff00
|
||||
orrne r2, r2, #0x0000ff00
|
||||
bic r0, r0, r2
|
||||
orr r0, r0, r1
|
||||
str r0, [ip, r3, lsr #SH2_DRAM_SHIFT]
|
||||
#else
|
||||
add ip, ip, r3, lsr #SH2_DRAM_SHIFT
|
||||
tst r1, #0x00ff0000
|
||||
lsrne r3, r1, #16
|
||||
strneb r3, [ip, #0]
|
||||
tst r1, #0xff000000
|
||||
lsrne r3, r1, #24
|
||||
strneb r3, [ip, #1]
|
||||
tst r1, #0x000000ff
|
||||
strneb r1, [ip, #2]
|
||||
tst r1, #0x0000ff00
|
||||
lsrne r3, r1, #8
|
||||
strneb r3, [ip, #3]
|
||||
#endif
|
||||
bx lr
|
||||
|
||||
.pool
|
||||
|
||||
@ vim:filetype=armasm
|
||||
|
|
@ -229,7 +229,7 @@ void sh2_peripheral_reset(SH2 *sh2)
|
|||
// SH2 internal peripheral memhandlers
|
||||
// we keep them in little endian format
|
||||
|
||||
u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
|
||||
u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2)
|
||||
{
|
||||
u8 *r = (void *)sh2->peri_regs;
|
||||
u32 d;
|
||||
|
|
@ -242,7 +242,7 @@ u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
|
|||
return d;
|
||||
}
|
||||
|
||||
u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
|
||||
u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
|
||||
{
|
||||
u16 *r = (void *)sh2->peri_regs;
|
||||
u32 d;
|
||||
|
|
@ -255,7 +255,7 @@ u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
|
|||
return d;
|
||||
}
|
||||
|
||||
u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
|
||||
u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2)
|
||||
{
|
||||
u32 d;
|
||||
a &= 0x1fc;
|
||||
|
|
|
|||
|
|
@ -958,9 +958,9 @@ void p32x_dreq1_trigger(void);
|
|||
void p32x_timers_recalc(void);
|
||||
void p32x_timers_do(unsigned int m68k_slice);
|
||||
void sh2_peripheral_reset(SH2 *sh2);
|
||||
unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);
|
||||
unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);
|
||||
unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);
|
||||
unsigned int REGPARM(2) sh2_peripheral_read8(unsigned int a, SH2 *sh2);
|
||||
unsigned int REGPARM(2) sh2_peripheral_read16(unsigned int a, SH2 *sh2);
|
||||
unsigned int REGPARM(2) sh2_peripheral_read32(unsigned int a, SH2 *sh2);
|
||||
void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);
|
||||
void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);
|
||||
void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue