mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
32x: drc: handlers wip
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@826 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
c18edb34e6
commit
80599a42db
10 changed files with 830 additions and 116 deletions
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@ -30,8 +30,15 @@
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#define A_COND_NE 0x1
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#define A_COND_MI 0x4
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#define A_COND_PL 0x5
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#define A_COND_LS 0x9
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#define A_COND_LE 0xd
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/* unified conditions */
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#define DCOND_EQ A_COND_EQ
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#define DCOND_NE A_COND_NE
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#define DCOND_MI A_COND_MI
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#define DCOND_PL A_COND_PL
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/* addressing mode 1 */
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#define A_AM1_LSL 0
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#define A_AM1_LSR 1
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@ -49,6 +56,7 @@
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#define A_OP_RSB 0x3
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#define A_OP_ADD 0x4
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#define A_OP_TST 0x8
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#define A_OP_TEQ 0x9
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#define A_OP_CMP 0xa
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#define A_OP_ORR 0xc
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#define A_OP_MOV 0xd
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@ -71,37 +79,43 @@
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#define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
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#define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
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#define EOP_MOV_REG(s, rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
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#define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_TST_REG( rn, shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
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#define EOP_MOV_IMM_C(cond,rd, ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
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#define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
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#define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
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#define EOP_MOV_REG2(s, rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
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#define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
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#define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
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#define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
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#define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_TST_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
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#define EOP_TEQ_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
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#define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
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#define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
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#define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
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#define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
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#define EOP_MOV_REG2(s,rd, rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
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#define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
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#define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
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#define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
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#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
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#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
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#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
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#define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
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#define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
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#define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
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#define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
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#define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
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#define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
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#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
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#define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
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#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
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#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
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#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
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#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
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#define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG( rn, 0,A_AM1_LSL,rm)
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#define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
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#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
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#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
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#define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_LSL,rm)
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#define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_ROR,rm)
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#define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
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#define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
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#define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG(A_COND_AL, rn, 0,A_AM1_LSL,rm)
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#define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_LSL,rs)
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#define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_ROR,rs)
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#define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
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#define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
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/* addressing mode 2 */
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#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
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@ -169,13 +183,15 @@
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#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
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static void emith_op_imm(int cond, int op, int r, unsigned int imm)
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static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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{
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int ror2, rn = r;
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int ror2, rd = r, rn = r;
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u32 v;
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if (op == A_OP_MOV)
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rn = 0;
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else if (op == A_OP_TST || op == A_OP_TEQ)
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rd = 0;
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else if (imm == 0)
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return;
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@ -184,7 +200,7 @@ static void emith_op_imm(int cond, int op, int r, unsigned int imm)
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for (; v && !(v & 3); v >>= 2)
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ror2--;
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EOP_C_DOP_IMM(cond, op, 0, rn, r, ror2 & 0x0f, v & 0xff);
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EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
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if (op == A_OP_MOV) {
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op = A_OP_ORR;
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@ -226,6 +242,13 @@ static int emith_xbranch(int cond, void *target, int is_call)
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}
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// fake "simple" or "short" jump - using cond insns instead
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#define EMITH_SJMP_START(cond) \
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(void)(cond)
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#define EMITH_SJMP_END(cond) \
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(void)(cond)
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#define EMITH_CONDITIONAL(code, is_nonzero) { \
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u32 val, cond, *ptr; \
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cond = (is_nonzero) ? A_COND_NE : A_COND_EQ; \
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@ -236,17 +259,67 @@ static int emith_xbranch(int cond, void *target, int is_call)
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EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | (val & 0xffffff)); \
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}
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#define emith_move_r_r(dst, src) \
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EOP_MOV_REG_SIMPLE(dst, src)
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#define emith_move_r_r(d, s) \
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EOP_MOV_REG_SIMPLE(d, s)
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#define emith_add_r_r(d, s) \
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EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_sub_r_r(d, s) \
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EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_teq_r_r(d, s) \
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EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
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#define emith_subf_r_r(d, s) \
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EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
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#define emith_move_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, A_OP_MOV, r, imm)
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emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
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#define emith_add_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, A_OP_ADD, r, imm)
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emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
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#define emith_sub_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, A_OP_SUB, r, imm)
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emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
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#define emith_bic_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
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#define emith_or_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
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// note: use 8bit imm only
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#define emith_tst_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_TST, r, imm)
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#define emith_subf_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
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#define emith_add_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_ADD, r, imm)
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#define emith_sub_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_SUB, r, imm)
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#define emith_or_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_ORR, r, imm)
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#define emith_lsl(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
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#define emith_lsr(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
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#define emith_asrf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
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#define emith_mul(d, s1, s2) { \
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if ((d) != (s1)) /* rd != rm limitation */ \
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EOP_MUL(d, s1, s2); \
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else \
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EOP_MUL(d, s2, s1); \
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}
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#define emith_ctx_read(r, offs) \
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EOP_LDR_IMM(r, CONTEXT_REG, offs)
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#define emith_ctx_write(r, offs) \
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EOP_STR_IMM(r, CONTEXT_REG, offs)
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#define emith_clear_msb(d, s, count) { \
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u32 t; \
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if ((count) <= 8) { \
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t = (count) - 8; \
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t = (0xff << t) & 0xff; \
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EOP_BIC_IMM(d,s,8/2,t); \
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} else if ((count) >= 24) { \
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t = (count) - 24; \
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t = 0xff >> t; \
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EOP_AND_IMM(d,s,0,t); \
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} else { \
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EOP_MOV_REG_LSL(d,s,count); \
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EOP_MOV_REG_LSR(d,d,count); \
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} \
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}
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#define emith_sext(d, s, bits) { \
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EOP_MOV_REG_LSL(d,s,32 - (bits)); \
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EOP_MOV_REG_ASR(d,d,32 - (bits)); \
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}
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#define host_arg2reg(rd, arg) \
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rd = arg
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// upto 4 args
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#define emith_pass_arg_r(arg, reg) \
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EOP_MOV_REG_SIMPLE(arg, reg)
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@ -274,9 +371,29 @@ static int emith_xbranch(int cond, void *target, int is_call)
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emith_jump_cond(A_COND_AL, target)
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/* SH2 drc specific */
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#define emith_test_t() { \
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#define emith_sh2_test_t() { \
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int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
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EOP_TST_IMM(r, 0, 1); \
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}
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#define emith_sh2_dtbf_loop() { \
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int cr, rn; \
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tmp = rcache_get_tmp(); \
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cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); \
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emith_sub_r_imm(rn, 1); /* sub rn, #1 */ \
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emith_bic_r_imm(cr, 1); /* bic cr, #1 */ \
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emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
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cycles = 0; \
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emith_asrf(tmp, cr, 2+12); /* movs tmp, cr, asr #2+12 */ \
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EOP_MOV_IMM_C(A_COND_MI,tmp,0,0); /* movmi tmp, #0 */ \
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emith_lsl(cr, cr, 20); /* mov cr, cr, lsl #20 */ \
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emith_lsr(cr, cr, 20); /* mov cr, cr, lsr #20 */ \
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emith_subf_r_r(rn, tmp); /* subs rn, tmp */ \
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EOP_RSB_IMM_C(A_COND_LS,tmp,rn,0,0); /* rsbls tmp, rn, #0 */ \
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EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp,A_AM1_LSL,12+2); /* orrls cr,tmp,lsl #12+2 */\
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EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1); /* orrls cr, #1 */ \
|
||||
EOP_MOV_IMM_C(A_COND_LS,rn,0,0); /* movls rn, #0 */ \
|
||||
rcache_free_tmp(tmp); \
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,20 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
|
|||
|
||||
#define CONTEXT_REG xBP
|
||||
|
||||
#define IOP_JE 0x74
|
||||
#define IOP_JNE 0x75
|
||||
#define IOP_JBE 0x76
|
||||
#define IOP_JA 0x77
|
||||
#define IOP_JS 0x78
|
||||
#define IOP_JNS 0x79
|
||||
#define IOP_JLE 0x7e
|
||||
|
||||
// unified conditions (we just use rel8 jump instructions for x86)
|
||||
#define DCOND_EQ IOP_JE
|
||||
#define DCOND_NE IOP_JNE
|
||||
#define DCOND_MI IOP_JS // MInus
|
||||
#define DCOND_PL IOP_JNS // PLus or zero
|
||||
|
||||
#define EMIT_PTR(ptr, val, type) \
|
||||
*(type *)(ptr) = val
|
||||
|
||||
|
|
@ -25,24 +39,148 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
|
|||
EMIT_MODRM(mod, r, rm); \
|
||||
}
|
||||
|
||||
#define JMP8_POS(ptr) \
|
||||
ptr = tcache_ptr; \
|
||||
tcache_ptr += 2
|
||||
|
||||
#define JMP8_EMIT(op, ptr) \
|
||||
EMIT_PTR(ptr, op, u8); \
|
||||
EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
|
||||
|
||||
#define emith_move_r_r(dst, src) \
|
||||
EMIT_OP_MODRM(0x8b, 3, dst, src)
|
||||
|
||||
#define emith_add_r_r(d, s) \
|
||||
EMIT_OP_MODRM(0x01, 3, s, d)
|
||||
|
||||
#define emith_sub_r_r(d, s) \
|
||||
EMIT_OP_MODRM(0x29, 3, s, d)
|
||||
|
||||
#define emith_or_r_r(d, s) \
|
||||
EMIT_OP_MODRM(0x09, 3, s, d)
|
||||
|
||||
#define emith_eor_r_r(d, s) \
|
||||
EMIT_OP_MODRM(0x31, 3, s, d)
|
||||
|
||||
// fake teq - test equivalence - get_flags(d ^ s)
|
||||
#define emith_teq_r_r(d, s) { \
|
||||
emith_push(d); \
|
||||
emith_eor_r_r(d, s); \
|
||||
emith_pop(d); \
|
||||
}
|
||||
|
||||
// _r_imm
|
||||
#define emith_move_r_imm(r, imm) { \
|
||||
EMIT_OP(0xb8 + (r)); \
|
||||
EMIT(imm, u32); \
|
||||
}
|
||||
|
||||
#define emith_add_r_imm(r, imm) { \
|
||||
EMIT_OP_MODRM(0x81, 3, 0, r); \
|
||||
#define emith_arith_r_imm(op, r, imm) { \
|
||||
EMIT_OP_MODRM(0x81, 3, op, r); \
|
||||
EMIT(imm, u32); \
|
||||
}
|
||||
|
||||
#define emith_sub_r_imm(r, imm) { \
|
||||
EMIT_OP_MODRM(0x81, 3, 5, r); \
|
||||
// 2 - adc, 3 - sbb, 6 - xor, 7 - cmp
|
||||
#define emith_add_r_imm(r, imm) \
|
||||
emith_arith_r_imm(0, r, imm)
|
||||
|
||||
#define emith_or_r_imm(r, imm) \
|
||||
emith_arith_r_imm(1, r, imm)
|
||||
|
||||
#define emith_and_r_imm(r, imm) \
|
||||
emith_arith_r_imm(4, r, imm)
|
||||
|
||||
#define emith_sub_r_imm(r, imm) \
|
||||
emith_arith_r_imm(5, r, imm)
|
||||
|
||||
#define emith_tst_r_imm(r, imm) { \
|
||||
EMIT_OP_MODRM(0xf7, 3, 0, r); \
|
||||
EMIT(imm, u32); \
|
||||
}
|
||||
|
||||
// fake
|
||||
#define emith_bic_r_imm(r, imm) \
|
||||
emith_arith_r_imm(4, r, ~(imm))
|
||||
|
||||
// fake conditionals (using SJMP instead)
|
||||
#define emith_add_r_imm_c(cond, r, imm) { \
|
||||
(void)(cond); \
|
||||
emith_arith_r_imm(0, r, imm); \
|
||||
}
|
||||
|
||||
#define emith_or_r_imm_c(cond, r, imm) { \
|
||||
(void)(cond); \
|
||||
emith_arith_r_imm(1, r, imm); \
|
||||
}
|
||||
|
||||
#define emith_sub_r_imm_c(cond, r, imm) { \
|
||||
(void)(cond); \
|
||||
emith_arith_r_imm(5, r, imm); \
|
||||
}
|
||||
|
||||
// shift
|
||||
#define emith_shift(op, d, s, cnt) { \
|
||||
if (d != s) \
|
||||
emith_move_r_r(d, s); \
|
||||
EMIT_OP_MODRM(0xc1, 3, op, d); \
|
||||
EMIT(cnt, u8); \
|
||||
}
|
||||
|
||||
#define emith_asr(d, s, cnt) \
|
||||
emith_shift(7, d, s, cnt)
|
||||
|
||||
#define emith_lsl(d, s, cnt) \
|
||||
emith_shift(4, d, s, cnt)
|
||||
|
||||
// misc
|
||||
#define emith_push(r) \
|
||||
EMIT_OP(0x50 + (r))
|
||||
|
||||
#define emith_pop(r) \
|
||||
EMIT_OP(0x58 + (r))
|
||||
|
||||
#define emith_neg_r(r) \
|
||||
EMIT_OP_MODRM(0xf7, 3, 3, r)
|
||||
|
||||
#define emith_clear_msb(d, s, count) { \
|
||||
u32 t = (u32)-1; \
|
||||
t >>= count; \
|
||||
if (d != s) \
|
||||
emith_move_r_r(d, s); \
|
||||
emith_and_r_imm(d, t); \
|
||||
}
|
||||
|
||||
#define emith_sext(d, s, bits) { \
|
||||
emith_lsl(d, s, 32 - (bits)); \
|
||||
emith_asr(d, d, 32 - (bits)); \
|
||||
}
|
||||
|
||||
// XXX: stupid mess
|
||||
#define emith_mul(d, s1, s2) { \
|
||||
int rmr; \
|
||||
if (d != xAX) \
|
||||
emith_push(xAX); \
|
||||
if ((s1) == xAX) \
|
||||
rmr = s2; \
|
||||
else if ((s2) == xAX) \
|
||||
rmr = s1; \
|
||||
else { \
|
||||
emith_move_r_r(xAX, s1); \
|
||||
rmr = s2; \
|
||||
} \
|
||||
emith_push(xDX); \
|
||||
EMIT_OP_MODRM(0xf7, 3, 4, rmr); /* MUL rmr */ \
|
||||
emith_pop(xDX); \
|
||||
if (d != xAX) { \
|
||||
emith_move_r_r(d, xAX); \
|
||||
emith_pop(xAX); \
|
||||
} \
|
||||
}
|
||||
|
||||
// "flag" instructions are the same
|
||||
#define emith_subf_r_imm emith_sub_r_imm
|
||||
#define emith_subf_r_r emith_sub_r_r
|
||||
|
||||
// XXX: offs is 8bit only
|
||||
#define emith_ctx_read(r, offs) { \
|
||||
EMIT_OP_MODRM(0x8b, 1, r, xBP); \
|
||||
|
|
@ -66,15 +204,16 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
|
|||
EMIT(disp, u32); \
|
||||
}
|
||||
|
||||
#define EMITH_CONDITIONAL(code, is_nonzero) { \
|
||||
u8 *ptr = tcache_ptr; \
|
||||
tcache_ptr = tcache_ptr + 2; \
|
||||
code; \
|
||||
EMIT_PTR(ptr, ((is_nonzero) ? 0x75 : 0x74), u8); \
|
||||
EMIT_PTR(ptr + 1, (tcache_ptr - (ptr + 2)), u8); \
|
||||
// "simple" or "short" jump
|
||||
#define EMITH_SJMP_START(cond) { \
|
||||
u8 *cond_ptr; \
|
||||
JMP8_POS(cond_ptr)
|
||||
|
||||
#define EMITH_SJMP_END(cond) \
|
||||
JMP8_EMIT(cond, cond_ptr); \
|
||||
}
|
||||
|
||||
#define arg2reg(rd, arg) \
|
||||
#define host_arg2reg(rd, arg) \
|
||||
switch (arg) { \
|
||||
case 0: rd = xAX; break; \
|
||||
case 1: rd = xDX; break; \
|
||||
|
|
@ -83,25 +222,46 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
|
|||
|
||||
#define emith_pass_arg_r(arg, reg) { \
|
||||
int rd = 7; \
|
||||
arg2reg(rd, arg); \
|
||||
host_arg2reg(rd, arg); \
|
||||
emith_move_r_r(rd, reg); \
|
||||
}
|
||||
|
||||
#define emith_pass_arg_imm(arg, imm) { \
|
||||
int rd = 7; \
|
||||
arg2reg(rd, arg); \
|
||||
host_arg2reg(rd, arg); \
|
||||
emith_move_r_imm(rd, imm); \
|
||||
}
|
||||
|
||||
/* SH2 drc specific */
|
||||
#define emith_test_t() { \
|
||||
if (reg_map_g2h[SHR_SR] == -1) { \
|
||||
EMIT_OP_MODRM(0xf6, 1, 0, 5); \
|
||||
EMIT(SHR_SR * 4, u8); \
|
||||
EMIT(0x01, u8); /* test [ebp+SHR_SR], byte 1 */ \
|
||||
} else { \
|
||||
EMIT_OP_MODRM(0xf7, 3, 0, reg_map_g2h[SHR_SR]); \
|
||||
EMIT(0x01, u16); /* test <reg>, word 1 */ \
|
||||
} \
|
||||
#define emith_sh2_test_t() { \
|
||||
int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
|
||||
EMIT_OP_MODRM(0xf6, 3, 0, t); \
|
||||
EMIT(0x01, u8); /* test <reg>, byte 1 */ \
|
||||
}
|
||||
|
||||
#define emith_sh2_dtbf_loop() { \
|
||||
u8 *jmp0; /* negative cycles check */ \
|
||||
u8 *jmp1; /* unsinged overflow check */ \
|
||||
int cr, rn; \
|
||||
tmp = rcache_get_tmp(); \
|
||||
cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
|
||||
rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
|
||||
emith_sub_r_imm(rn, 1); \
|
||||
emith_sub_r_imm(cr, (cycles+1) << 12); \
|
||||
cycles = 0; \
|
||||
emith_asr(tmp, cr, 2+12); \
|
||||
JMP8_POS(jmp0); /* no negative cycles */ \
|
||||
emith_move_r_imm(tmp, 0); \
|
||||
JMP8_EMIT(IOP_JNS, jmp0); \
|
||||
emith_and_r_imm(cr, 0xffe); \
|
||||
emith_subf_r_r(rn, tmp); \
|
||||
JMP8_POS(jmp1); /* no overflow */ \
|
||||
emith_neg_r(rn); /* count left */ \
|
||||
emith_lsl(rn, rn, 2+12); \
|
||||
emith_or_r_r(cr, rn); \
|
||||
emith_or_r_imm(cr, 1); \
|
||||
emith_move_r_imm(rn, 0); \
|
||||
JMP8_EMIT(IOP_JA, jmp1); \
|
||||
rcache_free_tmp(tmp); \
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue