mirror of
https://github.com/RaySollium99/picodrive.git
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svp compiler: more ops, idle detection
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@364 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
b9c1d0129a
commit
d274c33b6b
3 changed files with 192 additions and 54 deletions
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@ -8,12 +8,11 @@ static unsigned int *block_table[0x5090/2];
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static unsigned int *block_table_iram[15][0x800/2];
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static unsigned int *tcache_ptr = NULL;
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static int had_jump = 0;
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static int nblocks = 0;
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static int iram_context = 0;
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#ifndef ARM
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#define DUMP_BLOCK 0x84a
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#define DUMP_BLOCK 0x1d7c
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unsigned int tcache[512*1024];
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void regfile_load(void){}
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void regfile_store(void){}
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@ -25,7 +24,7 @@ void regfile_store(void){}
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#define GET_PC() rPC
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#define GET_PPC_OFFS() (GET_PC()*2 - 2)
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#define SET_PC(d) { had_jump = 1; rPC = d; } /* must return to dispatcher after this */
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#define SET_PC(d) { rPC = d; } /* must return to dispatcher after this */
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//#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
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//#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
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//#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
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@ -548,13 +547,13 @@ static struct
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#define CRREG_AL (1 << 16)
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static u32 const_regb = 0; /* bitfield of known register values */
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static u32 dirty_regb = 0; /* known vals, which need to be flushed (only r0-r7) */
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static u32 dirty_regb = 0; /* known vals, which need to be flushed (only P, r0-r7) */
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/* known values of host regs.
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* -1 - unknown
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* 00000-0ffff - 16bit value
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* 10000-1ffff - base reg (r7) + 16bit val
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* 20000 - means reg (low) eq AH
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* -1 - unknown
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* 000000-00ffff - 16bit value
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* 100000-10ffff - base reg (r7) + 16bit val
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* 0r0000 - means reg (low) eq gr[r].h
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*/
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static int hostreg_r[4];
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@ -569,7 +568,7 @@ static void hostreg_clear(void)
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{
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int i;
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for (i = 0; i < 4; i++)
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if (hostreg_r[i] == 0x20000) hostreg_r[i] = -1;
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if (hostreg_r[i] == (SSP_A<<16)) hostreg_r[i] = -1;
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}
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@ -584,8 +583,20 @@ static void tr_mov16(int r, int val)
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}
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}
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/* update P, if needed. Trashes r1 */
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static void tr_flush_dirty_P(void)
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{
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// TODO: const regs
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if (!(dirty_regb & CRREG_P)) return;
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EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
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EOP_MOV_REG_LSL( 1, 4, 16); // mov r1, r4, lsl #16
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EOP_MOV_REG_ASR( 1, 1, 15); // mov r1, r1, asr #15
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EOP_MUL(10, 1, 10); // mul r10, r1, r10
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dirty_regb &= ~CRREG_P;
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}
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/* write dirty r0-r7 to host regs. Nothing is trashed */
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static void tr_flush_dirty(void)
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static void tr_flush_dirty_pr(void)
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{
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int i, ror = 0, reg;
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dirty_regb >>= 8;
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@ -611,9 +622,9 @@ static void tr_bank_read(int addr) /* word addr 0-0x1ff */
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if (addr&1) {
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int breg = 7;
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if (addr > 0x7f) {
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if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
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if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
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EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
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hostreg_r[1] = 0x10000|((addr&0x180)<<1);
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hostreg_r[1] = 0x100000|((addr&0x180)<<1);
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}
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breg = 1;
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}
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@ -629,9 +640,9 @@ static void tr_bank_write(int addr)
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{
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int breg = 7;
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if (addr > 0x7f) {
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if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
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if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
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EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
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hostreg_r[1] = 0x10000|((addr&0x180)<<1);
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hostreg_r[1] = 0x100000|((addr&0x180)<<1);
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}
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breg = 1;
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}
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@ -677,10 +688,86 @@ static void tr_ptrr_mod(int r, int mod, int need_modulo)
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//@ r7: SSP context
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//@ r10: P
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// write r0 to general reg handlers. Trashes r1
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static void tr_r0_unhandled(void)
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static void tr_GR0_to_r0(void)
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{
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printf("unhandled\n");
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tr_mov16(0, 0xffff);
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}
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static void tr_X_to_r0(void)
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{
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if (hostreg_r[0] != (SSP_X<<16)) {
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EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
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hostreg_r[0] = SSP_X<<16;
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}
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}
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static void tr_Y_to_r0(void)
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{
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// TODO..
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if (hostreg_r[0] != (SSP_Y<<16)) {
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EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
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hostreg_r[0] = SSP_Y<<16;
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}
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}
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static void tr_A_to_r0(void)
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{
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if (hostreg_r[0] != (SSP_A<<16)) {
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EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
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hostreg_r[0] = SSP_A<<16;
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}
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}
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static void tr_ST_to_r0(void)
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{
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// VR doesn't need much accuracy here..
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EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
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EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
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hostreg_r[0] = -1;
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}
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static void tr_STACK_to_r0(void)
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{
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// 448
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EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
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EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
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EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
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EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
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EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
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hostreg_r[0] = hostreg_r[1] = -1;
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}
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static void tr_PC_to_r0(void)
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{
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tr_mov16(0, const_regs.gr[SSP_PC].h);
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}
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static void tr_P_to_r0(void)
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{
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tr_flush_dirty_P();
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EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
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hostreg_r[0] = -1;
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}
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typedef void (tr_read_func)(void);
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static tr_read_func *tr_read_funcs[8] =
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{
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tr_GR0_to_r0,
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tr_X_to_r0,
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tr_Y_to_r0,
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tr_A_to_r0,
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tr_ST_to_r0,
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tr_STACK_to_r0,
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tr_PC_to_r0,
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tr_P_to_r0
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};
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// write r0 to general reg handlers. Trashes r1
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static void tr_unhandled(void)
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{
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printf("unhandled @ %04x\n", const_regs.gr[SSP_PC].h<<1);
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exit(1);
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}
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@ -694,6 +781,7 @@ static void tr_r0_to_X(void)
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EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
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EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
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EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
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dirty_regb |= CRREG_P; // touching X or Y makes P dirty.
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}
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static void tr_r0_to_Y(void)
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@ -701,14 +789,14 @@ static void tr_r0_to_Y(void)
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EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
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EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
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EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
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dirty_regb |= CRREG_P;
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}
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static void tr_r0_to_A(void)
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{
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EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
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EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsl #16 @ AL
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EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
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EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
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hostreg_r[0] = 0x20000;
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}
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static void tr_r0_to_ST(void)
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@ -725,16 +813,16 @@ static void tr_r0_to_STACK(void)
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// 448
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EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
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EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
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EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #26
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EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
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EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
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EOP_ADD_IMM(6, 6, 24/2, 0x20); // add r6, r6, #1<<29
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EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
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hostreg_r[1] = -1;
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}
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static void tr_r0_to_PC(void)
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{
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EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
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EOP_STR_IMM(0,7,0x400+6*4); // str r0, [r7, #(0x400+6*8)]
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EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
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hostreg_r[1] = -1;
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}
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@ -749,28 +837,45 @@ static tr_write_func *tr_write_funcs[8] =
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tr_r0_to_ST,
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tr_r0_to_STACK,
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tr_r0_to_PC,
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tr_r0_unhandled
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tr_unhandled
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};
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static int translate_op(unsigned int op, int *pc, int imm)
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{
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u32 tmpv;
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u32 tmpv, tmpv2;
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int ret = 0;
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const_regs.gr[SSP_PC].h = *pc;
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switch (op >> 9)
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{
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// ld d, s
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case 0x00:
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if (op == 0) { ret++; break; } // nop
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break;
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tmpv = op & 0xf; // src
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tmpv2 = (op >> 4) & 0xf; // dst
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if (tmpv >= 8 || tmpv2 >= 8) return -1; // TODO
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if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
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tr_flush_dirty_P();
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EOP_MOV_REG_SIMPLE(5, 10);
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const_regb &= ~(CRREG_A|CRREG_AL);
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ret++; break;
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}
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tr_read_funcs[tmpv]();
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tr_write_funcs[tmpv2]();
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if (const_regb & (1 << tmpv)) {
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const_regs.gr[tmpv2].h = const_regs.gr[tmpv].h;
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const_regb |= 1 << tmpv2;
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} else
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const_regb &= ~(1 << tmpv2);
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ret++; break;
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// ld a, adr
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case 0x03:
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tr_bank_read(op&0x1ff);
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tr_r0_to_A();
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const_regb &= ~CRREG_A;
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hostreg_r[0] = 0x20000;
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hostreg_r[0] = SSP_A<<16;
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ret++; break;
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// ldi d, imm
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@ -792,14 +897,16 @@ static int translate_op(unsigned int op, int *pc, int imm)
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emit_mov_const(0, tmpv);
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EOP_LDR_IMM(1,7,0x484); // ldr r0, [r7, #0x484] // emu_status
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EOP_STR_IMM(0,7,0x400+14*4); // PMC
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// TODO: do this only on reads
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if (tmpv == 0x187f04) { // fe08
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// reads on fe06, fe08; next op is ld -,
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if ((tmpv == 0x187f03 || tmpv == 0x187f04) && (PROGRAM(*pc) & 0xfff0) == 0)
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{
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int flag = (tmpv == 0x187f03) ? (SSP_WAIT_30FE06) : (SSP_WAIT_30FE08);
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EOP_LDR_IMM(0,7,0x490); // dram_ptr
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EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00
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EOP_LDRH_IMM(0,0,8); // ldrh r0, [r0, #8]
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EOP_TST_REG_SIMPLE(0,0);
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,SSP_WAIT_30FE08>>8); // orr r1, r1, #SSP_WAIT_30FE08
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orr r1, r1, #SSP_WAIT_30FE08
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}
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EOP_ORR_IMM(1,1,0,SSP_PMC_SET); // orr r1, r1, #SSP_PMC_SET
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EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
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@ -818,9 +925,9 @@ static int translate_op(unsigned int op, int *pc, int imm)
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{
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tmpv = (op>>2) & 3; // direct addressing
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if (op & 0x100) {
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if (hostreg_r[1] != 0x10200) {
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if (hostreg_r[1] != 0x100200) {
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EOP_ADD_IMM(1,7,30/2,0x200>>2); // add r1, r7, 0x200
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hostreg_r[1] = 0x10200;
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hostreg_r[1] = 0x100200;
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}
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EOP_STRH_IMM(0,1,tmpv<<1); // str r0, [r1, {0,2,4,6}]
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} else {
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@ -849,13 +956,35 @@ static int translate_op(unsigned int op, int *pc, int imm)
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// ld adr, a
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case 0x07:
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if (hostreg_r[0] != 0x20000) {
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if (hostreg_r[0] != (SSP_A<<16)) {
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EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ A
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hostreg_r[0] = 0x20000;
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hostreg_r[0] = SSP_A<<16;
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}
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tr_bank_write(op&0x1ff);
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ret++; break;
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// ld d, ri
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case 0x09: {
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int r, reg;
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r = (op&3) | ((op>>6)&4); // src
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tmpv2 = (op >> 4) & 0xf; // dst
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if (tmpv2 >= 8) tr_unhandled();
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if (const_regb & (1 << (r+8))) {
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tr_mov16(0, const_regs.r[r]);
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const_regs.gr[tmpv2].h = const_regs.r[r];
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const_regb |= 1 << tmpv2;
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} else {
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reg = (r < 4) ? 8 : 9;
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if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
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EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
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hostreg_r[0] = -1;
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const_regb &= ~(1 << tmpv2);
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}
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tr_write_funcs[tmpv2]();
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ret++; break;
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}
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// ldi ri, simm
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case 0x0c ... 0x0f:
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tmpv = (op>>8)&7;
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@ -872,14 +1001,15 @@ static void *translate_block(int pc)
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{
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unsigned int op, op1, imm, ccount = 0;
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unsigned int *block_start;
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int ret;
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int ret, ret_prev = -1;
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// create .pool
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//*tcache_ptr++ = (u32) in_funcs; // -1 func pool
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printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
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block_start = tcache_ptr;
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const_regb = dirty_regb = 0;
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const_regb = 0;
|
||||
dirty_regb = CRREG_P;
|
||||
hostreg_clear();
|
||||
|
||||
emit_block_prologue();
|
||||
|
|
@ -897,7 +1027,7 @@ static void *translate_block(int pc)
|
|||
ret = translate_op(op, &pc, imm);
|
||||
if (ret <= 0)
|
||||
{
|
||||
tr_flush_dirty();
|
||||
tr_flush_dirty_pr();
|
||||
|
||||
emit_mov_const(0, op);
|
||||
|
||||
|
|
@ -908,7 +1038,9 @@ static void *translate_block(int pc)
|
|||
// dump PC
|
||||
emit_pc_dump(pc);
|
||||
|
||||
emit_interpreter_call(in_funcs[op1]);
|
||||
if (ret_prev > 0) emit_call(regfile_store);
|
||||
emit_call(in_funcs[op1]);
|
||||
emit_call(regfile_load);
|
||||
|
||||
if (in_funcs[op1] == NULL) {
|
||||
printf("NULL func! op=%08x (%02x)\n", op, op1);
|
||||
|
|
@ -916,6 +1048,7 @@ static void *translate_block(int pc)
|
|||
}
|
||||
ccount++;
|
||||
hostreg_clear();
|
||||
dirty_regb |= CRREG_P;
|
||||
}
|
||||
else
|
||||
ccount += ret;
|
||||
|
|
@ -925,9 +1058,10 @@ static void *translate_block(int pc)
|
|||
(op & 0xf0) == 0x60)) { // ld PC
|
||||
break;
|
||||
}
|
||||
ret_prev = ret;
|
||||
}
|
||||
|
||||
tr_flush_dirty();
|
||||
tr_flush_dirty_pr();
|
||||
emit_block_epilogue(ccount + 1);
|
||||
*tcache_ptr++ = 0xffffffff; // end of block
|
||||
//printf(" %i inst\n", icount);
|
||||
|
|
@ -977,9 +1111,9 @@ int ssp1601_dyn_startup(void)
|
|||
void ssp1601_dyn_reset(ssp1601_t *ssp)
|
||||
{
|
||||
ssp1601_reset_local(ssp);
|
||||
ssp->rom_ptr = (unsigned int) Pico.rom;
|
||||
ssp->iram_ptr = (unsigned int) svp->iram_rom;
|
||||
ssp->dram_ptr = (unsigned int) svp->dram;
|
||||
ssp->ptr_rom = (unsigned int) Pico.rom;
|
||||
ssp->ptr_iram = (unsigned int) svp->iram_rom;
|
||||
ssp->ptr_dram = (unsigned int) svp->dram;
|
||||
}
|
||||
|
||||
void ssp1601_dyn_run(int cycles)
|
||||
|
|
@ -1011,8 +1145,6 @@ void ssp1601_dyn_run(int cycles)
|
|||
trans_entry = (void *) block_table[rPC];
|
||||
}
|
||||
|
||||
had_jump = 0;
|
||||
|
||||
//printf("enter %04x\n", rPC<<1);
|
||||
cycles -= trans_entry();
|
||||
//printf("leave %04x\n", rPC<<1);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue