mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
32x: drc: first implementation finished, no more interpreter dep
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@832 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
4b315c210a
commit
f0d7b1faa1
11 changed files with 397 additions and 161 deletions
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@ -189,8 +189,11 @@
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#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
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#define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \
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EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
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#define EOP_C_B(cond,l,signed_immed_24) \
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EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
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EOP_C_B_PTR(tcache_ptr,cond,l,signed_immed_24)
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#define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
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#define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
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@ -205,6 +208,9 @@
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#define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_C_SMLAL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
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#define EOP_C_MRS(cond,rd) \
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@ -308,6 +314,15 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) \
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EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSR,lsrimm)
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#define emith_or_r_r_lsl(d, s, lslimm) \
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emith_or_r_r_r_lsl(d, d, s, lslimm)
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#define emith_eor_r_r_lsr(d, s, lsrimm) \
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emith_eor_r_r_r_lsr(d, d, s, lsrimm)
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#define emith_or_r_r_r(d, s1, s2) \
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emith_or_r_r_r_lsl(d, s1, s2, 0)
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@ -390,6 +405,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_or_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_ORR, r, imm)
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#define emith_eor_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_EOR, r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_BIC, r, imm)
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@ -459,6 +477,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_mul_s64(dlo, dhi, s1, s2) \
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EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
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#define emith_mula_s64(dlo, dhi, s1, s2) \
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EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
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// misc
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#define emith_ctx_read(r, offs) \
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EOP_LDR_IMM(r, CONTEXT_REG, offs)
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@ -466,27 +487,42 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_ctx_write(r, offs) \
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EOP_STR_IMM(r, CONTEXT_REG, offs)
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#define emith_clear_msb(d, s, count) { \
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#define emith_clear_msb_c(cond, d, s, count) { \
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u32 t; \
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if ((count) <= 8) { \
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t = (count) - 8; \
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t = (0xff << t) & 0xff; \
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EOP_BIC_IMM(d,s,8/2,t); \
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EOP_C_DOP_IMM(cond,A_OP_BIC,0,s,d,8/2,t); \
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} else if ((count) >= 24) { \
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t = (count) - 24; \
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t = 0xff >> t; \
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EOP_AND_IMM(d,s,0,t); \
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EOP_C_DOP_IMM(cond,A_OP_AND,0,s,d,0,t); \
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} else { \
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EOP_MOV_REG_LSL(d,s,count); \
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EOP_MOV_REG_LSR(d,d,count); \
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EOP_MOV_REG(cond,0,d,s,A_AM1_LSL,count); \
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EOP_MOV_REG(cond,0,d,d,A_AM1_LSR,count); \
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} \
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}
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#define emith_clear_msb(d, s, count) \
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emith_clear_msb_c(A_COND_AL, d, s, count)
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#define emith_sext(d, s, bits) { \
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EOP_MOV_REG_LSL(d,s,32 - (bits)); \
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EOP_MOV_REG_ASR(d,d,32 - (bits)); \
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}
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#define JMP_POS(ptr) \
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ptr = tcache_ptr; \
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tcache_ptr += sizeof(u32)
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#define JMP_EMIT(cond, ptr) { \
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int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
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EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
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}
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// _r_r
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// put bit0 of r0 to carry
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#define emith_set_carry(r0) \
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EOP_TST_REG(A_COND_AL,r0,r0,A_AM1_LSR,1) /* shift out to carry */ \
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@ -564,3 +600,24 @@ static int emith_xbranch(int cond, void *target, int is_call)
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emith_bic_r_imm_c(A_COND_CC, srr, 1); \
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} \
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}
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/*
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* if Q
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* t = carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* T ^= t
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*/
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#define emith_sh2_div1_step(rn, rm, sr) { \
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void *jmp0, *jmp1; \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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JMP_POS(jmp0); /* beq do_sub */ \
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emith_addf_r_r(rn, rm); \
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emith_eor_r_imm_c(A_COND_CS, sr, T); \
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JMP_POS(jmp1); /* b done */ \
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JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */ \
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emith_subf_r_r(rn, rm); \
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emith_eor_r_imm_c(A_COND_CC, sr, T); \
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JMP_EMIT(A_COND_AL, jmp1); /* done: */ \
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}
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@ -1,5 +1,5 @@
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/*
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* note about silly things like emith_or_r_r_r_lsl:
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* note about silly things like emith_eor_r_r_r:
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* these are here because the compiler was designed
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* for ARM as it's primary target.
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*/
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@ -9,6 +9,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define CONTEXT_REG xBP
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#define IOP_JMP 0xeb
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#define IOP_JO 0x70
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#define IOP_JNO 0x71
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#define IOP_JB 0x72
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@ -56,6 +57,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define EMIT_MODRM(mod,r,rm) \
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EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
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#define EMIT_SIB(scale,index,base) \
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EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
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#define EMIT_OP_MODRM(op,mod,r,rm) { \
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EMIT_OP(op); \
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EMIT_MODRM(mod, r, rm); \
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@ -139,14 +143,22 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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} \
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}
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#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) { \
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// _r_r_shift
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#define emith_or_r_r_lsl(d, s, lslimm) { \
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int tmp_ = rcache_get_tmp(); \
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emith_lsl(tmp_, s2, lslimm); \
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emith_or_r_r(tmp_, s1); \
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emith_move_r_r(d, tmp_); \
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emith_lsl(tmp_, s, lslimm); \
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emith_or_r_r(d, tmp_); \
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rcache_free_tmp(tmp_); \
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}
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// d != s
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#define emith_eor_r_r_lsr(d, s, lsrimm) { \
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emith_push(s); \
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emith_lsr(s, s, lsrimm); \
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emith_eor_r_r(d, s); \
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emith_pop(s); \
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}
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// _r_imm
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#define emith_move_r_imm(r, imm) { \
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EMIT_OP(0xb8 + (r)); \
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@ -200,6 +212,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_or_r_imm(r, imm); \
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}
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#define emith_eor_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_eor_r_imm(r, imm); \
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}
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#define emith_sub_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_sub_r_imm(r, imm); \
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@ -264,11 +281,22 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_and_r_imm(d, t); \
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}
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#define emith_clear_msb_c(cond, d, s, count) { \
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(void)(cond); \
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emith_clear_msb(d, s, count); \
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}
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#define emith_sext(d, s, bits) { \
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emith_lsl(d, s, 32 - (bits)); \
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emith_asr(d, d, 32 - (bits)); \
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}
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#define emith_setc(r) { \
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EMIT_OP(0x0f); \
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EMIT(0x92, u8); \
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EMIT_MODRM(3, 0, r); /* SETC r */ \
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}
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// put bit0 of r0 to carry
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#define emith_set_carry(r0) { \
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emith_tst_r_imm(r0, 1); /* clears C */ \
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@ -318,6 +346,19 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_mul(d, s1, s2) \
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emith_mul_(4, d, -1, s1, s2)
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// (dlo,dhi) += signed(s1) * signed(s2)
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#define emith_mula_s64(dlo, dhi, s1, s2) { \
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emith_push(dhi); \
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emith_push(dlo); \
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emith_mul_(5, dlo, dhi, s1, s2); \
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EMIT_OP_MODRM(0x03, 0, dlo, 4); \
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EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
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EMIT_OP_MODRM(0x13, 1, dhi, 4); \
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EMIT_SIB(0, 4, 4); \
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EMIT(4, u8); /* adc dhi, [esp+4] */ \
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emith_add_r_imm(xSP, 4*2); \
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}
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// "flag" instructions are the same
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#define emith_subf_r_imm emith_sub_r_imm
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#define emith_addf_r_r emith_add_r_r
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@ -357,6 +398,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT(disp, u32); \
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}
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#define emith_call_cond(cond, ptr) \
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emith_call(ptr)
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// "simple" or "short" jump
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#define EMITH_SJMP_START(cond) { \
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u8 *cond_ptr; \
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@ -429,11 +473,31 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_carry_to_t(srr, is_sub) { \
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int tmp_ = rcache_get_tmp(); \
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EMIT_OP(0x0f); \
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EMIT(0x92, u8); \
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EMIT_MODRM(3, 0, tmp_); /* SETC */ \
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emith_setc(tmp_); \
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emith_bic_r_imm(srr, 1); \
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EMIT_OP_MODRM(0x08, 3, tmp_, srr); /* OR srrl, tmpl */ \
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rcache_free_tmp(tmp_); \
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}
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/*
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* if Q
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* t = carry(Rn += Rm)
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* else
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* t = carry(Rn -= Rm)
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* T ^= t
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*/
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#define emith_sh2_div1_step(rn, rm, sr) { \
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u8 *jmp0, *jmp1; \
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int tmp_ = rcache_get_tmp(); \
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emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
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JMP8_POS(jmp0); /* je do_sub */ \
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emith_add_r_r(rn, rm); \
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JMP8_POS(jmp1); /* jmp done */ \
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JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */ \
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emith_sub_r_r(rn, rm); \
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JMP8_EMIT(IOP_JMP, jmp1);/* done: */ \
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emith_setc(tmp_); \
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EMIT_OP_MODRM(0x30, 3, tmp_, sr); /* T = Q1 ^ Q2 (byte) */ \
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rcache_free_tmp(tmp_); \
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}
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@ -1,6 +1,7 @@
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/*
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* vim:shiftwidth=2:expandtab
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*/
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#include <stddef.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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@ -125,6 +126,9 @@ static temp_reg_t reg_temp[] = {
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#define Q 0x00000100
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#define M 0x00000200
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#define Q_SHIFT 8
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#define M_SHIFT 9
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typedef enum {
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SHR_R0 = 0, SHR_SP = 15,
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SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
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@ -517,6 +521,58 @@ static void emit_indirect_indexed_write(int rx, int ry, int wr, int size)
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emit_memhandler_write(size);
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}
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// read @Rn, @rm
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static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
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{
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int tmp;
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rcache_clean();
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rcache_get_reg_arg(0, rn);
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tmp = emit_memhandler_read(size);
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emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
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rcache_free_tmp(tmp);
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tmp = rcache_get_reg(rn, RC_GR_RMW);
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emith_add_r_imm(tmp, 1 << size);
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rcache_clean();
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rcache_get_reg_arg(0, rm);
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*rmr = emit_memhandler_read(size);
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*rnr = rcache_get_tmp();
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emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
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tmp = rcache_get_reg(rm, RC_GR_RMW);
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emith_add_r_imm(tmp, 1 << size);
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}
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// fixup for saturated MAC, to be called from generated code
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// FIXME: statically alloced regs need to be fixed
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static void sh2_macl_sat_fixup(void)
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{
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if ((signed int)sh2->mach < 0 && sh2->mach < 0xffff8000)
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{
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sh2->mach = 0x00008000;
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sh2->macl = 0x00000000;
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}
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else if ((signed int)sh2->mach > 0 && sh2->mach > 0x00007fff)
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{
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sh2->mach = 0x00007fff;
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sh2->macl = 0xffffffff;
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}
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}
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static void sh2_macw_sat_fixup(void)
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{
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signed int t = sh2->mach;
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if (t < -1 || (t == -1 && !(sh2->macl & 0x80000000)))
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{
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sh2->mach = 0xffffffff; // ?
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sh2->macl = 0x80000000;
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}
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else if (t > 0 || (t == 0 && (sh2->macl & 0x80000000)))
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{
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sh2->mach = 0x7fffffff;
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sh2->macl = 0xffffffff;
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}
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}
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#define DELAYED_OP \
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delayed_op = 2
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@ -546,7 +602,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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int op, delayed_op = 0, test_irq = 0;
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int tcache_id = 0, blkid = 0;
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int cycles = 0;
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u32 tmp, tmp2, tmp3, tmp4;
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u32 tmp, tmp2, tmp3, tmp4, sr;
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// validate PC
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tmp = sh2->pc >> 29;
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|
|
@ -771,8 +827,27 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
rcache_free_tmp(tmp);
|
||||
goto end_op;
|
||||
case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
|
||||
// TODO
|
||||
break;
|
||||
emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
|
||||
tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
|
||||
tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
|
||||
/* MS 16 MAC bits unused if saturated */
|
||||
emith_tst_r_imm(tmp3, S);
|
||||
EMITH_SJMP_START(DCOND_EQ);
|
||||
emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
|
||||
EMITH_SJMP_END(DCOND_EQ);
|
||||
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
|
||||
emith_mula_s64(tmp3, tmp4, tmp, tmp2);
|
||||
rcache_free_tmp(tmp);
|
||||
rcache_free_tmp(tmp2);
|
||||
rcache_clean();
|
||||
tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
|
||||
emith_tst_r_imm(tmp3, S);
|
||||
EMITH_SJMP_START(DCOND_EQ);
|
||||
emith_call_cond(DCOND_NE, sh2_macl_sat_fixup);
|
||||
EMITH_SJMP_END(DCOND_EQ);
|
||||
rcache_invalidate();
|
||||
cycles += 3;
|
||||
goto end_op;
|
||||
}
|
||||
goto default_;
|
||||
|
||||
|
|
@ -869,7 +944,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
|
||||
emith_lsr(tmp, tmp, 16);
|
||||
emith_or_r_r_r_lsl(tmp, tmp, tmp2, 16);
|
||||
emith_or_r_r_lsl(tmp, tmp2, 16);
|
||||
goto end_op;
|
||||
case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
|
||||
case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
|
||||
|
|
@ -935,8 +1010,37 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
}
|
||||
goto end_op;
|
||||
case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
|
||||
// TODO
|
||||
break;
|
||||
// Q1 = carry(Rn = (Rn << 1) | T)
|
||||
// if Q ^ M
|
||||
// Q2 = carry(Rn += Rm)
|
||||
// else
|
||||
// Q2 = carry(Rn -= Rm)
|
||||
// Q = M ^ Q1 ^ Q2
|
||||
// T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
|
||||
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_set_carry(sr);
|
||||
emith_adcf_r_r(tmp2, tmp2);
|
||||
emith_carry_to_t(sr, 0); // keep Q1 in T for now
|
||||
tmp4 = rcache_get_tmp();
|
||||
emith_and_r_r_imm(tmp4, sr, M);
|
||||
emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
|
||||
rcache_free_tmp(tmp4);
|
||||
// add or sub, invert T if carry to get Q1 ^ Q2
|
||||
// in: (Q ^ M) passed in Q, Q1 in T
|
||||
emith_sh2_div1_step(tmp2, tmp3, sr);
|
||||
emith_bic_r_imm(sr, Q);
|
||||
emith_tst_r_imm(sr, M);
|
||||
EMITH_SJMP_START(DCOND_EQ);
|
||||
emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
|
||||
EMITH_SJMP_END(DCOND_EQ);
|
||||
emith_tst_r_imm(sr, T);
|
||||
EMITH_SJMP_START(DCOND_EQ);
|
||||
emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
|
||||
EMITH_SJMP_END(DCOND_EQ);
|
||||
emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
|
||||
goto end_op;
|
||||
case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
|
||||
tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
|
||||
|
|
@ -1248,7 +1352,6 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
}
|
||||
if (tmp2 == SHR_SR) {
|
||||
emith_write_sr(tmp);
|
||||
emit_move_r_imm32(SHR_PC, pc);
|
||||
test_irq = 1;
|
||||
} else {
|
||||
tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
|
||||
|
|
@ -1257,7 +1360,24 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
goto end_op;
|
||||
case 0x0f:
|
||||
// MAC @Rm+,@Rn+ 0100nnnnmmmm1111
|
||||
break; // TODO
|
||||
emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
|
||||
emith_sext(tmp, tmp, 16);
|
||||
emith_sext(tmp2, tmp2, 16);
|
||||
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
|
||||
tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
|
||||
emith_mula_s64(tmp3, tmp4, tmp, tmp2);
|
||||
rcache_free_tmp(tmp);
|
||||
rcache_free_tmp(tmp2);
|
||||
rcache_clean();
|
||||
// XXX: MACH should be untouched when S is set?
|
||||
tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
|
||||
emith_tst_r_imm(tmp3, S);
|
||||
EMITH_SJMP_START(DCOND_EQ);
|
||||
emith_call_cond(DCOND_NE, sh2_macw_sat_fixup);
|
||||
EMITH_SJMP_END(DCOND_EQ);
|
||||
rcache_invalidate();
|
||||
cycles += 2;
|
||||
goto end_op;
|
||||
}
|
||||
goto default_;
|
||||
|
||||
|
|
@ -1315,9 +1435,9 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
tmp3 = rcache_get_tmp();
|
||||
tmp4 = rcache_get_tmp();
|
||||
emith_lsr(tmp3, tmp, 16);
|
||||
emith_or_r_r_r_lsl(tmp3, tmp3, tmp, 24);
|
||||
emith_or_r_r_lsl(tmp3, tmp, 24);
|
||||
emith_and_r_r_imm(tmp4, tmp, 0xff00);
|
||||
emith_or_r_r_r_lsl(tmp3, tmp3, tmp4, 8);
|
||||
emith_or_r_r_lsl(tmp3, tmp4, 8);
|
||||
emith_rol(tmp2, tmp3, 16);
|
||||
rcache_free_tmp(tmp4);
|
||||
if (tmp == tmp2)
|
||||
|
|
@ -1429,8 +1549,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
/////////////////////////////////////////////
|
||||
case 0x09:
|
||||
// MOV.W @(disp,PC),Rn 1001nnnndddddddd
|
||||
// TODO
|
||||
goto default_;
|
||||
rcache_clean();
|
||||
tmp = rcache_get_tmp_arg(0);
|
||||
emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2);
|
||||
tmp = emit_memhandler_read(1);
|
||||
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
|
||||
emith_sext(tmp2, tmp, 16);
|
||||
rcache_free_tmp(tmp);
|
||||
goto end_op;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
case 0x0a:
|
||||
|
|
@ -1557,8 +1683,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
/////////////////////////////////////////////
|
||||
case 0x0d:
|
||||
// MOV.L @(disp,PC),Rn 1101nnnndddddddd
|
||||
// TODO
|
||||
goto default_;
|
||||
rcache_clean();
|
||||
tmp = rcache_get_tmp_arg(0);
|
||||
emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3);
|
||||
tmp = emit_memhandler_read(2);
|
||||
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
|
||||
emith_move_r_r(tmp2, tmp);
|
||||
rcache_free_tmp(tmp);
|
||||
goto end_op;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
case 0x0e:
|
||||
|
|
@ -1569,11 +1701,15 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
|
||||
default:
|
||||
default_:
|
||||
elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
|
||||
sh2->is_slave ? 's' : 'm', op, pc - 2);
|
||||
#ifdef DRC_DEBUG_INTERP
|
||||
emit_move_r_imm32(SHR_PC, pc - 2);
|
||||
rcache_flush();
|
||||
emith_pass_arg_r(0, CONTEXT_REG);
|
||||
emith_pass_arg_imm(1, op);
|
||||
emith_call(sh2_do_op);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1582,10 +1718,12 @@ end_op:
|
|||
emit_move_r_r(SHR_PC, SHR_PPC);
|
||||
|
||||
if (test_irq && delayed_op != 2) {
|
||||
if (!delayed_op)
|
||||
emit_move_r_imm32(SHR_PC, pc);
|
||||
rcache_flush();
|
||||
emith_pass_arg_r(0, CONTEXT_REG);
|
||||
emith_call(sh2_test_irq);
|
||||
break;
|
||||
goto end_block_btf;
|
||||
}
|
||||
if (delayed_op == 1)
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@
|
|||
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
|
||||
|
||||
//int sh2_icount;
|
||||
SH2 *sh2;
|
||||
//SH2 *sh2;
|
||||
|
||||
#if 0
|
||||
INLINE UINT8 RB(offs_t A)
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ typedef unsigned char UINT8;
|
|||
|
||||
#include "sh2.c"
|
||||
|
||||
#ifndef DRC_TMP
|
||||
#ifndef DRC_SH2
|
||||
|
||||
void sh2_execute(SH2 *sh2_, int cycles)
|
||||
{
|
||||
|
|
@ -48,6 +48,7 @@ void sh2_execute(SH2 *sh2_, int cycles)
|
|||
{
|
||||
UINT32 opcode;
|
||||
|
||||
/* FIXME: Darxide doesn't like this */
|
||||
if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
|
||||
{
|
||||
if (sh2->pending_irl > sh2->pending_int_irq)
|
||||
|
|
@ -102,7 +103,7 @@ void sh2_execute(SH2 *sh2_, int cycles)
|
|||
sh2->cycles_done += cycles - sh2->icount;
|
||||
}
|
||||
|
||||
#else // DRC_TMP
|
||||
#else // DRC_SH2
|
||||
|
||||
#ifdef __i386__
|
||||
#define REGPARM(x) __attribute__((regparm(x)))
|
||||
|
|
@ -110,7 +111,7 @@ void sh2_execute(SH2 *sh2_, int cycles)
|
|||
#define REGPARM(x)
|
||||
#endif
|
||||
|
||||
// tmp
|
||||
// drc debug
|
||||
void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode)
|
||||
{
|
||||
sh2 = sh2_;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
|
||||
#define I 0xf0
|
||||
|
||||
SH2 *sh2; // active sh2
|
||||
|
||||
int sh2_init(SH2 *sh2, int is_slave)
|
||||
{
|
||||
int ret = 0;
|
||||
|
|
|
|||
|
|
@ -11,20 +11,20 @@ typedef struct
|
|||
unsigned int gbr, vbr; // 50
|
||||
unsigned int mach, macl; // 58
|
||||
|
||||
// interpreter stuff
|
||||
int icount; // 60 cycles left in current timeslice
|
||||
unsigned int ea;
|
||||
unsigned int delay;
|
||||
unsigned int test_irq;
|
||||
|
||||
// common
|
||||
const void *read8_map; // 70
|
||||
const void *read8_map; // 60
|
||||
const void *read16_map;
|
||||
const void **write8_tab;
|
||||
const void **write16_tab;
|
||||
|
||||
// drc stuff
|
||||
//void **pc_hashtab; // 80
|
||||
int drc_tmp; // 70
|
||||
|
||||
// interpreter stuff
|
||||
int icount; // cycles left in current timeslice
|
||||
unsigned int ea;
|
||||
unsigned int delay;
|
||||
unsigned int test_irq;
|
||||
|
||||
int pending_level; // MAX(pending_irl, pending_int_irq)
|
||||
int pending_irl;
|
||||
|
|
@ -37,7 +37,7 @@ typedef struct
|
|||
unsigned int cycles_done;
|
||||
} SH2;
|
||||
|
||||
extern SH2 *sh2; // active sh2
|
||||
extern SH2 *sh2; // active sh2. XXX: consider removing
|
||||
|
||||
int sh2_init(SH2 *sh2, int is_slave);
|
||||
void sh2_finish(SH2 *sh2);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue