10 commits

Author	SHA1	Message	Date
kub	18c95d9f57	sh2 drc, fix for SH2 T handling in Mips/RiscV	2020-06-25 16:49:17 +02:00
kub	c815b1bc59	sh2 drc, backend 32/64 bit compatibility fixes for Mips/RiscV	2020-06-23 23:34:07 +02:00
kub	8bb489470a	sh2 drc, add powerpc64le backend	2020-06-19 00:14:28 +02:00
kub	0e12269073	sh2 drc: optimize T bit handling for A64	2019-12-21 22:49:41 +01:00
kub	a5e51c16e6	sh2 drc: fix speed regression	2019-12-13 18:23:03 +01:00
kub	4f992bf541	sh2 drc, tentative MIPS32/64 Release 2 support	2019-12-02 22:31:14 +01:00
kub	57d863cb87	sh2 drc: bug fixing	2019-11-27 22:08:14 +01:00
kub	f1da0a362f	sh2 drc: fixed some RISC-V bugs	2019-11-20 01:01:33 +01:00
kub	f2d19ddf2a	sh2 drc, small improvements and bug fixes for code emitters	2019-11-19 21:59:44 +01:00
kub	f7a453816e	sh2 drc: RISC-V (RV64IM) code emitter, some work on MIPS64	2019-11-13 21:58:48 +01:00